Quotables
"The horse is here to stay, the automobile is only a novelty - fad."
President of Michigan Savings Bank ; 1903
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7436077 | Semiconductor device and method of manufacturing the same A semiconductor device includes a first surface faced to a mounting board when the semiconductor device is placed over the mounting board and a second surface opposed to the first surface. The semiconductor device also includes a position reference portion which is ... | 10/14/2008 |
| 7429522 | Dicing die-bonding film A dicing die-bonding film has a supporting substrate, an adhesive layer formed on the supporting substrate, and a die-bonding adhesive layer formed on the adhesive layer, and further has a mark for recognizing the position of the die-bonding adhesive layer. It is po... | 09/30/2008 |
| 7422914 | Fabrication method of semiconductor integrated circuit device A memory test is carried out on semiconductor integrated circuit devices including a semiconductor memory at low cost with efficiency. In a test burn-in system, twenty-four test boards are processed in sequence with time differences, and the test boards are circulat... | 09/09/2008 |
| 7411294 | Display device having misalignment detection pattern for detecting misalignment between conductive layer and insulating layer A display device includes a display panel, and the circuit substrate is separately formed and positioned different from the array substrate of the display panel and connected to the display panel. The circuit substrate includes an insulating substrate, a conductive ... | 08/12/2008 |
| 7408265 | Use of a dual-tone resist to form photomasks including alignment mark protection, intermediate semiconductor device structures and bulk semiconductor device substrates An alignment mark mask element protects an underlying alignment mark during subsequent processing of a fabrication substrate. The alignment mark mask element is formed concurrent with formation of a photomask from a dual-tone photoresist that exhibits a pattern reve... | 08/05/2008 |
| 7402914 | Semiconductor device featuring overlay-mark used in photolithography process In a semiconductor device, an insulating layer formed on a substrate and a wiring pattern layer is formed on the insulating layer. A lower mark element is defined as a groove formed in the insulating layer, and defines an overlay mark in conjunction with an upper ma... | 07/22/2008 |
| 7399990 | Wafer-level package having test terminal A wafer-level package includes a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit each provided with test chip terminals and non test chip terminals, at least one external connection termin... | 07/15/2008 |
| 7393754 | Tape carrier type semiconductor device and method of producing the same A tape carrier type semiconductor device comprising: a long flexible insulating tape; and a plurality of semiconductor devices sequentially arranged on one surface of the tape, wherein each semiconductor device has a wiring pattern and a semiconductor element, and w... | 07/01/2008 |
| 7390682 | Method for testing metal-insulator-metal capacitor structures under high temperature at wafer level A test methodology is provided for testing metal-insulator-metal (MIM) capacitor structures under high temperatures at the wafer level. A resistor is formed on a region of dielectric isolation material formed in a semiconductor substrate. The MIM capacitor is formed... | 06/24/2008 |
| 7390722 | System and method for using an oxidation process to create a stepper alignment structure on semiconductor wafers An oxidation process is used to produce a positional reference structure on a semiconductor wafer. A photolithographic mask layer used to define the positional reference structure can be combined with a photolithographic mask layer used to define an active device la... | 06/24/2008 |
| 7390723 | Alignment method of using alignment marks on wafer edge A method for stacking and bonding wafers in precision alignment by detecting alignment marks provided on wafer edges, comprising the steps of: (a) providing at least a first wafer having at least a first pattern and at least a second pattern disposed on the cross-se... | 06/24/2008 |
| 7382038 | Semiconductor wafer and method for making the same A semiconductor wafer includes a plurality of active circuit die areas, each of which being bordered by a dicing line through which the plurality of active circuit die areas are separated from each other by mechanical wafer dicing. WAT pads are disposed along the di... | 06/03/2008 |
| 7372150 | Semiconductor wafer having identification indication A semiconductor wafer including an identification indication is provided. The wafer includes a convex edge with an upper surface area and a lower surface area. The identification indication is in a marking region which is disposed on a lower side surface of the conv... | 05/13/2008 |
| 7368748 | Test pixel and test pixel array for evaluating pixel quality in CMOS image sensor A test pixel for use in a CMOS image sensor is employed to evaluate a pixel quality by modulating a contact chain. The test pixel for use the CMOS image sensor including: a test pixel active area corresponding to each unit pixel active area, wherein the unit pixel a... | 05/06/2008 |
| 7355291 | Overlay marks, methods of overlay mark design and methods of overlay measurements An overlay mark for determining the relative position between two or more successive layers of a substrate or between two or more separately generated patterns on a single layer of a substrate is disclosed. The overlay mark includes a plurality of coarsely segmented... | 04/08/2008 |
| 7355201 | Test structure for measuring electrical and dimensional characteristics A test structure includes first and second combs, at least a first pair of base nodes, and a second pair of finger nodes. The first comb includes a first base and a first plurality of fingers extending from the first base. The second comb includes a second base and ... | 04/08/2008 |
| 7352891 | Position detecting method There is provided a position detecting method for detecting a position of an object, on which an alignment mark including plural mark elements is formed. The method includes the steps of obtaining positional information indicative of each position of the plural mark... | 04/01/2008 |
| 7352001 | Method of editing a semiconductor die Resistance and capacitance are added to a prototype die to fix or identify performance issues with the integrated circuit formed in the die by forming a thin piece of silicon on the top surface of the die. For resistance, vias are formed to regions on the metal trac... | 04/01/2008 |
| 7348597 | Apparatus for performing high frequency electronic package testing Various apparatus for performing high frequency electronic package testing are disclosed. A test fixture assembly includes an electronics package having an interface structure, a mock-up IC, coupled to the interface structure for providing circuit connections, and a... | 03/25/2008 |
| 7342295 | Porogen material A porogen material for forming a dielectric porous film. The porogen material may include a silicon based dielectric precursor and a silicon containing porogen. The porous film may have a substantially uniform dielectric constant value throughout. Methods of forming... | 03/11/2008 |
| 7338885 | Alignment mark and method for manufacturing a semiconductor device having the same In a method for manufacturing a semiconductor device having an alignment mark, a buffer layer is formed on a substrate. A trench is formed at an isolation region of the substrate. The trench is filled with an insulating layer. An alignment groove is formed on the in... | 03/04/2008 |
| 7332360 | Early detection of metal wiring reliability using a noise spectrum The present invention generally provides an apparatus and a method for inspecting a substrate in a substrate processing system. In one aspect, a voltage or current source is used in conjunction with a power density receiving device, such as a spectrometer, to inspec... | 02/19/2008 |
| 7326973 | Method and an apparatus for a hard-coded bit value changeable in any layer of metal A method is disclosed to make a hard-coded bit in an integrated circuit on a semiconductor chip changeable in any one and only one metal layer of the semiconductor chip. In one embodiment, the method further comprising fabricating a cell on each metal layer of the s... | 02/05/2008 |
| 7317224 | Semiconductor device A semiconductor device includes a gate electrode GE electrically connected to a gate portion which is made of a polysilicon film provided in the inside of a plurality of grooves formed in a striped form along the direction of T of a chip region CA wherein the gate e... | 01/08/2008 |
| 7309925 | Dicing die-bonding film A dicing die-bonding film has a supporting substrate, an adhesive layer formed on the supporting substrate, and a die-bonding adhesive layer formed on the adhesive layer, and further has a mark for recognizing the position of the die-bonding adhesive layer. It is po... | 12/18/2007 |
| 7306957 | Fabrication method of semiconductor integrated circuit device A memory test is carried out on semiconductor integrated circuit devices including a semiconductor memory at low cost with efficiency. In a test burn-in system, twenty-four test boards are processed in sequence with time differences, and the test boards are circulat... | 12/11/2007 |
| 7291507 | Using a time invariant statistical process variable of a semiconductor chip as the chip identifier A method for providing an identifier for a semiconductor chip after the manufacture of the semiconductor chip using a fabrication process includes selecting one or more circuit elements formed on the semiconductor chip where each of the circuit elements having an el... | 11/06/2007 |
| 7288848 | Overlay mark for measuring and correcting alignment errors An overlay mark includes at least one hole array formed on a semiconductor substrate and at least one linear trench adjacent to the hole array. The hole array may be formed adjacent to the linear trench along a predetermined direction. When alignment errors among pa... | 10/30/2007 |
| 7282422 | Overlay key, method of manufacturing the same and method of measuring an overlay degree using the same An overlay key includes a first overlay key having a first main overlay pattern and a first auxiliary pattern, and a second overlay key having a second main overlay pattern and a second auxiliary overlay pattern, the second auxiliary overlay pattern formed at a loca... | 10/16/2007 |
| 7265454 | Semiconductor device and method of producing high contrast identification mark A semiconductor device (50) includes a semiconductor die (20) having a first surface (14) for forming electronic circuitry. A coating layer (16) formed on a second surface (15) of the semiconductor die has a color that contrasts wi... | 09/04/2007 |
| 7256478 | Notched compound semiconductor wafer There is provided a notched compound semiconductor crystal having the same specification even if it is turned over. With respect to a compound semiconductor wafer produced by slicing a compound semiconductor crystal having a crystal plane of (100) plane, the crystal... | 08/14/2007 |
| 7256477 | Notched compound semiconductor wafer There is provided a notched compound semiconductor crystal having the same specification even if it is turned over. With respect to a compound semiconductor wafer produced by slicing a compound semiconductor crystal having a crystal plane of (100) plane, the crystal... | 08/14/2007 |
| 7256476 | Notched compound semiconductor wafer There is provided a notched compound semiconductor crystal having the same specification even if it is turned over. With respect to a compound semiconductor wafer produced by slicing a compound semiconductor crystal having a crystal plane of (100) plane, the crystal... | 08/14/2007 |
| 7253519 | Chip packaging structure having redistribution layer with recess A chip structure comprising a chip, a redistribution layer, a second passivation layer and at least a bump is provided. The chip has a first passivation layer and at least a bonding pad. The first passivation layer exposes the bonding pad and has at least a recess. ... | 08/07/2007 |
| 7250318 | System and method for providing automated sample preparation for plan view transmission electron microscopy A system and method is described for providing automated sample preparation for plan view transmission electron microscopy. A sample wafer is microcleaved from a semiconductor wafer and mounted on a first support stub. Then the sample wafer is cut with an automated ... | 07/31/2007 |
| 7247952 | Optical targets An optical target is provided. In one embodiment, the target is formed on a substrate. The target includes a first layer deposited below a second layer on the substrate. The second layer is deposited below a third layer on the substrate. The first layer has a topogr... | 07/24/2007 |
| 7245029 | Semiconductor device, manufacturing method and mounting method of the semiconductor device, circuit board, and electronic apparatus To easily determine an orientation of a semiconductor device, a semiconductor device includes a substrate including electrode electrically connected to an integrated circuit, an external terminal electrically connected to the electrode, and a light transmissive insu... | 07/17/2007 |
| 7241664 | Alignment mark forming method, substrate in which devices are formed, and liquid discharging head using substrate A method of manufacturing functional elements by forming a plurality of functional elements each having a through-hole piercing a surface on a substrate. The method includes the steps of forming an alignment mark on a surface of the substrate in an area in which the... | 07/10/2007 |
| 7239024 | Semiconductor package with recess for die A semiconductor package is disclosed with a recess (51) for an integrated circuit die (52). The recess is made by bending or deforming all layers of a package substrate, and therefore the recess contains circuitry to connect to the integrated circuit d... | 07/03/2007 |
| 7238592 | Method of manufacturing a semiconductor device having an alignment mark A method of manufacturing a semiconductor device includes providing a substrate and forming a projecting alignment mark. The substrate includes an insulating layer and a semiconductor layer on the insulating layer, and the substrate includes device areas and a scrib... | 07/03/2007 |
