Class 257/E23.175 - Geometry or layout of interconnection structure (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E23.169. This subclass
No. of patents: 167
Last issue date: 10/14/2008

«First «Previous1 2 3 4 5 Next»Last»

Number	Title	Issue Date
7436072	Protected chip stack A protected chip stack having a first chip and a second chip on the first chip. A functional layer in at least the first chip or the second chip. On the first chip and on the second chip there is in each case a connecting element, the connecting element on the first...	10/14/2008
7436050	Semiconductor device having a flexible printed circuit To provide a thin film device which becomes possible to be formed in the portion which has been considered impossible to be provided with such device by the conventional technique, and to provide a semiconductor device which occupies small space and which has high s...	10/14/2008
7432597	Semiconductor device and method of manufacturing the same In a semiconductor device including a memory region and a logic region, one or more of a plurality of logic transistor connection plugs, buried in a first insulating layer and connected to a diffusion layer of a logic transistor, are left unconnected to a first inte...	10/07/2008
7411304	Semiconductor interconnect having conductive spring contacts An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor component. Each interconnect contact includes a compliant conductive layer ...	08/12/2008
7391117	Method for fabricating semiconductor components with conductive spring contacts An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor component. Each interconnect contact includes a compliant conductive layer ...	06/24/2008
7391122	Techniques for flip chip package migration Techniques for integrated circuit packaging in a flip chip configuration that ensures a migration path between related integrated circuits and utilizes core I/O (or area I/O) are provided. An integrated circuit, having a superset of functional circuit elements as co...	06/24/2008
7355272	Semiconductor device with stacked semiconductor chips of the same type A semiconductor device includes a wiring board, a first semiconductor chip (e.g. DRAM) that is flip-chip connected on the wiring board, a second semiconductor chip (e.g. DRAM) that is of the same type as the first semiconductor chip and is mounted face up on the fir...	04/08/2008
7332818	Multi-chip electronic package with reduced line skew and circuitized substrate for use therein An electronic package which includes a circuitized substrate having at least two electrical components positioned thereon. The package includes patterns of contact sites, each for having one of the components coupled thereto. The patterns of contact sites in turn ar...	02/19/2008
7327042	Interconnection structure of electric conductive wirings Accumulating spaces for conductive particles are formed in gaps of wiring patterns for conductive wirings which are disposed on a surface of a supporting body. When interconnecting a pair of interconnection objects having the respective wiring patterns via an anisot...	02/05/2008
7323785	Semiconductor device A through-electrode that penetrates a semiconductor substrate and that is insulatively separated from the semiconductor substrate includes an inner through-electrode, a quadrangular ring-shaped semiconductor, and an outer peripheral through-electrode. The quadrangul...	01/29/2008
7291916	Signal transmission structure and circuit substrate thereof A signal transmission structure suitable for a multi-layer circuit substrate comprising a core layer and at least a dielectric layer is provided. The signal transmission structure according to the present invention comprises a first via landing pad and a reference p...	11/06/2007
7250371	Reduction of feature critical dimensions A feature in a layer is provided. A photoresist layer is formed over the layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls, where the photoresist features have a first critical dimension. A conformal layer is deposited...	07/31/2007
7198980	Methods for assembling multiple semiconductor devices A multidie semiconductor device (MDSCD) package includes a generally planar interposer comprising a substrate with a central receptacle, upper surface conductors, and outer connectors on the lower surface of the interposer. Conductive vias connect upper surface cond...	04/03/2007
7180180	Stacked device underfill and a method of fabrication Numerous embodiments of a stacked device underfill and a method of formation are disclosed. In one embodiment, a method of forming stacked semiconductor device with an underfill comprises forming one or more layers of compliant material on at least a portion of the ...	02/20/2007
7112866	Method to form a cross network of air gaps within IMD layer The invention provides a new multilevel interconnect structure of air gaps in a layer of IMD. A first layer of dielectric is provided over a surface; the surface contains metal points of contact. Trenches are provided in this first layer of dielectric. The trenches ...	09/26/2006
7098541	Interconnect method for directly connected stacked integrated circuits A method and related configuration for stacking and interconnecting multiple identical integrated circuit semiconductor die. A die designed in accordance with the present invention can be directly interconnected with other identical die by placing a second die on a ...	08/29/2006
7084513	Semiconductor device having a plurality of semiconductor chips and method for manufacturing the same A semiconductor device includes a first semiconductor chip (5) having a first terminal (7) on one surface, a second semiconductor chip (1a) which is larger than the first semiconductor chip (5) and on which the first semiconductor ...	08/01/2006
6704248	High density power module incorporating passive components distributed in a substrate The present invention is directed towards a multilayered circuit module and a method for constructing such a module, wherein the module has passive components such as capacitors, inductors, transformers distributed into a ceramic substrate. This module pr...	03/09/2004
6682981	Stress controlled dielectric integrated circuit fabrication General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a sem...	01/27/2004
6665182	Module unit for memory modules and method for its production The invention relates to a module unit for memory modules and to a method for producing the module unit. A module unit of this type has at least one main module and submodules. The modules are arranged in a star-shaped manner and are arranged radially wit...	12/16/2003
6632705	Memory modules and packages using different orientations and terminal assignments A memory module and a method of packaging memory devices are provided. The method prepares semiconductor packages of the memory devices, each of which has external pins that include data pins and command signal pins, and mounts the packages on a printed c...	10/14/2003
6624703	Terminal arrangement for an electrical device This invention provides a terminal arrangement for an electrical device. The electrical device includes a ground terminal on its outer surface that has a relatively large surface area. The electrical device also includes a plurality of contact terminals t...	09/23/2003
6602735	Method of fabricating a semiconductor chip package with a lead frame and multiple integrated circuit chips A lead frame for a semiconductor chip package includes a frame body and at least two chip-receiving windows formed in the frame body. Each chip-receiving window receives a respective integrated circuit chip therein. A plurality of internal connection lead...	08/05/2003
6584004	Electronic circuit package An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and th...	06/24/2003
6577016	Semiconductor device having adhesive inflow preventing means A semiconductor device includes a print wiring board having a element mounting section, a wire connecting section and a wiring section for connecting the element mounting section with the wire connecting section, all of which are provided at least one by ...	06/10/2003
6563211	Semiconductor device for controlling electricity A semiconductor device for controlling electricity including a metal base plate and at least one insulating substrate. The insulating substrate includes an insulator plate, a back-side pattern on a back face of the insulator plate and bonded to the metal ...	05/13/2003
6521530	Composite interposer and method for producing a composite interposer A composite interposer for providing power and signal connections between an integrated circuit chip or chips and a substrate. The interposer includes a signal core formed from a conductive power/ground plane positioned between two dielectric layers. A me...	02/18/2003
6465336	Circuit and method for providing interconnections among individual integrated circuit chips in a multi-chip module A multi-chip module ("MCM") and methods of operation and manufacture thereof. The MCM includes: (1) a substrate for supporting a plurality of separate integrated circuit (IC) chips thereon, (2) first and second separate IC chips mounted on the substrate, ...	10/15/2002
6465085	Thin film wiring board and method for manufacturing the same, base substrate and method for manufacturing the same A dummy pad is formed through a polyimide insulating layer so as to be provided opposite to a via connecting pad formed on the surface of a ceramic substrate. A defect occurring in the via connecting pad is filled with a protrusion when the dummy pad is f...	10/15/2002
6459157	Semiconductor device and double-sided multi-chip package A semiconductor device has a circuit board, a main chip mounted on a first surface of the circuit board, a subchip mounted on a second surface of the circuit board, interface circuits distributed in the main chip along four sides of the main chip, respect...	10/01/2002
6444563	Method and apparatus for extending fatigue life of solder joints in a semiconductor device A ball grid array (BGA) or chips scale package (CSP) integrated circuit (IC) (20) is manufactured by first identifying the most unreliable solder ball joints in the IC. These worst case joints, or joints in the vicinity of the worst case joints, are chang...	09/03/2002
6441474	Semiconductor device and liquid crystal module adopting the same A semiconductor device of a TCP or COF configuration is provided, including semiconductor chips mounted on a tape, which realizes compact mounting of a plurality of semiconductor chips on a single tape. In order to so, a semiconductor chip having a length...	08/27/2002
6437253	Terminal structure to which an electronic component is to be bonded Connection terminals are provided on the upper surface of a film substrate. Each terminal comprises an electrodeconnecting part and a circular reinforcing part connected to the distal end of the electrode-connecting part. Connection electrodes are provide...	08/20/2002
6407343	Multilayer wiring board A wiring layer on which X-directional signal lines 20 to 22 are arranged is formed on a multilayer board. Rectangular power-source conductive patterns 10c are arranged each in which via holes 12c are formed longitudinally or in the wiring direction of the...	06/18/2002
6407344	Multilayer circuit board A multilayer circuit board comprising a plurality of laminated routing layers, which is used to mount thereon an electronic part, such as a semiconductor chip or device, provided with electrodes formed in a certain pattern, each of the routing layers bein...	06/18/2002
6388200	Electronic interconnection medium having offset electrical mesh plane An electrical interconnection medium is provided having first and second overlying interconnection layers. Each interconnection layer includes parallel conductors, and the conductors of the first and second interconnection layers are oriented orthogonally...	05/14/2002
6376917	Semiconductor device A semiconductor device is characterized by mixedly mount a logic chip, an analog chip, a memory chip, etc. by stacking them while stabilizing power supply lines and ground lines of each chip. The semiconductor device has an intermediate substrate having a...	04/23/2002
6353258	Semiconductor module A semiconductor module has a plurality of power semiconductor devices mounted on a substrate, and a metal foil for wiring is mounted on the substrate so that an asymmetric unit arrangement of the semiconductor devices is formed. In the device, all of the ...	03/05/2002
6316790	Active matrix assembly with light blocking layer over channel region Improved thin film transistors resistant to photo-induced current and having improved electrical contact between electrodes and the source or drain regions are provided. The thin film transistors formed in accordance with the invention are particularly we...	11/13/2001
6310303	Structure for printed circuit design A substrate structure for surface mount devices, including a plurality of substrate layers including at least a base layer and an outer layer; the base layer having a contact surface and a first array of conductive elements on the contact surface; the out...	10/30/2001

«First «Previous1 2 3 4 5 Next»Last»

PatentStorm

Quotables

PatentStorm News

Class 257/E23.175 - Geometry or layout of interconnection structure (EPO)