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| Number | Title | Issue Date |
| 7411295 | Circuit board, device mounting structure, device mounting method, and electronic apparatus A circuit board has a metal pattern that is formed on a surface of the circuit board to be connected with bumps in two-dimensional arrangement for mounting an electronic device that has the bumps. A plurality of the bumps which has even electrical potentials is elec... | 08/12/2008 |
| 7405474 | Low cost thermally enhanced semiconductor package In one embodiment, a device is packaged using a low-cost thermally enhanced ball grid array (LCTE-BGA) package. The device may include a die with its backside mounted to the bottom side of a multi-layer packaging substrate. Thermal vias may be formed through the sub... | 07/29/2008 |
| 7397118 | Ceramic chip-type electronic component and method of making the same A chip-type electronic component includes a ceramic chip body, an external electrode formed on the chip body, a conductive elastic resin film made of a mixture of metal powder and elastic resin and formed to cover the external electrode, and a metal plating film. Th... | 07/08/2008 |
| 7358609 | Semiconductor device A semiconductor device having a structure which can be manufactured with a higher yield includes a local interconnection layer 14 (a first interconnection layer) on a semiconductor substrate 10 and a global interconnection layer 18 (a second int... | 04/15/2008 |
| 7352061 | Flexible core for enhancement of package interconnect reliability An IC package is disclosed that comprises a core region disposed between upper and lower build-up layer regions. In one embodiment, the core region comprises a low modulus material. In an alternative embodiment the core region comprises a medium modulus material. In... | 04/01/2008 |
| 7340829 | Method for fabricating electrical connection structure of circuit board A method for fabricating an electrical connection structure of a circuit board is proposed. The circuit board is provided with a plurality of pads on a surface thereof and with a plurality of conductive structures therein for electrically connecting the pad. A plura... | 03/11/2008 |
| 7307346 | Final passivation scheme for integrated circuits A semiconductor device includes a substrate with an active area. A last level interconnect capping layer is disposed over the active area. A buffer layer/crack stop layer overlies the last level interconnect capping layer and a passivation layer overlies the buffer ... | 12/11/2007 |
| 7301230 | Circuit board with a thin-film layer configured to accommodate a passive element A laminating step includes a second step of laminating a second insulation layer on a conductive pattern last formed at a first step, roughening the surface of the laminated second insulation layer excluding a desired area, and forming a conductive layer on at least... | 11/27/2007 |
| 7287328 | Methods for distributed electrode injection Methods for injecting charge include providing a target comprising a first layer on a second layer, coupling a conductive base to the second layer, and providing a medium which is in contact with at least a portion of the first layer. An electrode is positioned to f... | 10/30/2007 |
| 7084513 | Semiconductor device having a plurality of semiconductor chips and method for manufacturing the same A semiconductor device includes a first semiconductor chip (5) having a first terminal (7) on one surface, a second semiconductor chip (1a) which is larger than the first semiconductor chip (5) and on which the first semiconductor ... | 08/01/2006 |
| 6704248 | High density power module incorporating passive components distributed in a substrate The present invention is directed towards a multilayered circuit module and a method for constructing such a module, wherein the module has passive components such as capacitors, inductors, transformers distributed into a ceramic substrate. This module pr... | 03/09/2004 |
| 6682981 | Stress controlled dielectric integrated circuit fabrication General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a sem... | 01/27/2004 |
| 6646342 | Semiconductor chip and multi-chip module A bare-chip IP of a multi-chip module and an external device of the multi-chip module are interfaced with each other through a dedicated I/O bare-chip IP. Each of the bare-chip IPs other than the dedicated I/O bare-chip IP is not provided with an interfac... | 11/11/2003 |
| 6627992 | Millimeter wave (MMW) transceiver module with transmitter, receiver and local oscillator frequency multiplier surface mounted chip set A millimeter wave (MMW) transceiver module includes a microwave monolithic integrated circuit (MMIC) transceiver chip set that is surface mounted on a circuit board. The MMIC transceiver chip set includes a receiver MMIC chip package, a transmitter MMIC c... | 09/30/2003 |
| 6610934 | Semiconductor module and method of making the device A multi-chip module including semiconductor devices and a wiring substrate for mounting the semiconductor devices in which the wiring substrate comprises a glass substrate having holes formed by sand blasting and a wiring layer formed on the surface of th... | 08/26/2003 |
| 6607939 | Method of making a multi-layer interconnect Methods and apparatus for increasing the yield achieved during high density interconnect (HDI) production. In particular, processes in which panels are tested to identify good cells/parts, good cells are removed from the panels, and new panels created ent... | 08/19/2003 |
| 6599637 | Silicon nitride composite substrate A Si3 N4 composite substrate which manifests no generation of cracking on the substrate even by mechanical shock or thermal shock, and is excellent in heat radiation property and heat-cycle-resistance property is obtained by using a ... | 07/29/2003 |
| 6583365 | Conductive pads layout for BGA packaging structure A conductive pad layout is implemented on a substrate for BGA packaging structure. The substrate has a top trace surface on which is attached a chip, and a bottom trace surface. The top trace surface includes a first contact pad, a second contact pad plac... | 06/24/2003 |
| 6560860 | Low temperature co-fired ceramic with improved registration A low temperature co-fired ceramic assembly (LTCC) with a constraining core to minimize shrinkage of outer ceramic layers during firing. The outer ceramic layers have high density circuit features. A ceramic core includes several ceramic layers. Several v... | 05/13/2003 |
| 6555763 | Multilayered circuit board for semiconductor chip module, and method of manufacturing the same A multilayered circuit board for a semiconductor chip module includes an underlying board, insulating layers, fixed-potential wiring layers, via holes, and metal layers. The underlying board has a major surface made of a metal material to which a fixed po... | 04/29/2003 |
| 6556453 | Electronic circuit housing with trench vias and method of fabrication therefor An electronic circuit package (400, FIG. 4) includes one or more trench vias (404, FIG. 4). Each trench via makes electrical contact with one or more terminals (526, FIG. 5) of a discrete device (520, FIG. 5) embedded within the package. A trench via can ... | 04/29/2003 |
| 6546622 | Printed-wiring substrate and method for fabricating the same A printed-wiring substrate 1 includes internal dielectric resin layers 12 and 14. A main-surface-side external dielectric resin layer 13 is formed on the internal dielectric resin layer 12 such that the surface thereof serves as a substrate main-surface 1... | 04/15/2003 |
| 6544638 | Electronic chip package An electronic chip package is provided having a laminated substrate. The laminated substrate includes at least one conductive layer and at least one dielectric layer which is bonded to the conductive layer. The dielectric layer has a glass transition temp... | 04/08/2003 |
| 6526654 | Method of producing double-sided circuit board The method comprises forming a plurality of wiring pattern layers on the front surface of a substrate. In the process of forming the wiring pattern layers, an insulator protection film keeps covering over the wiring pattern on the back surface of the subs... | 03/04/2003 |
| 6521530 | Composite interposer and method for producing a composite interposer A composite interposer for providing power and signal connections between an integrated circuit chip or chips and a substrate. The interposer includes a signal core formed from a conductive power/ground plane positioned between two dielectric layers. A me... | 02/18/2003 |
| 6518516 | Multilayered laminate A multilayered laminate, substructures and associated methods of fabrication are presented. The multilayered laminate includes in sequential order: (a) a first intermediate layer having microvias and conductive lands; (b) a plurality of signal/power plane... | 02/11/2003 |
| 6509640 | Integral capacitor using embedded enclosure for effective electromagnetic radiation reduction In one embodiment of the invention, an integral capacitor includes a power plane, a ground plane, and a dielectric layer. The power plane has a power surface and a power periphery. The power plane couples power to signals of an integrated circuit operatin... | 01/21/2003 |
| 6509529 | Isolated flip chip of BGA to minimize interconnect stress due to thermal mismatch A wiring substrate with reduced thermal expansion stress. A wiring substrate, such as a laminated PWB, thin film circuit, lead frame, or chip carrier accepts an integrated circuit, such as a die, a flip chip, or ball grid array package. The wiring substra... | 01/21/2003 |
| 6503645 | Dielectric ceramic composition and ceramic electronic component A dielectric ceramic composition is comprised of a dielectric ceramic component represented by the formula: Ba(Zrx Zny Taz) Ow, wherein, on a molar basis, 0.01ࣘxࣘ0.06, 0.29ࣘyࣘ0.34, ... | 01/07/2003 |
| 6495772 | High performance dense wire for printed circuit board A method and structure for implementing dense wiring, in printed circuit board or chip carrier applications, which provides superior electrical characteristics while preserving the system resistance and characteristic impedance requirements. The dense wir... | 12/17/2002 |
| 6469378 | Power semiconductor module of high isolation strength A power semiconductor module achieves high isolation strength from a base through selectively positioning a plurality of metal coatings on first and second surfaces and positioning edges of the plurality to beneficially reduce the field strength tangentia... | 10/22/2002 |
| 6465085 | Thin film wiring board and method for manufacturing the same, base substrate and method for manufacturing the same A dummy pad is formed through a polyimide insulating layer so as to be provided opposite to a via connecting pad formed on the surface of a ceramic substrate. A defect occurring in the via connecting pad is filled with a protrusion when the dummy pad is f... | 10/15/2002 |
| 6461896 | Process for mounting electronic device and semiconductor device An electronic device comprising a semiconductor chip which is fixed to the mounting face of a wiring board through an adhesive and in which external terminals are electrically connected with electrode pads of the wiring board through bump electrodes. Rece... | 10/08/2002 |
| 6455936 | Integrated circuit assembly having interposer with a compliant layer An integrated circuit assembly includes a base board, an interposer, and an array of solder balls electrically and structurally interconnecting the interposer and the base board. The interposer has a backbone layer having a backbone stiffness, a first com... | 09/24/2002 |
| 6440641 | Deposited thin film build-up layer dimensions as a method of relieving stress in high density interconnect printed wiring board substrates The present invention provides a method for controlling the mechanical stresses at the interfaces of the metal and dielectric materials in the printed wiring substrates of high density interconnects. The invention enables the minimization of cracking due ... | 08/27/2002 |
| 6442041 | MCM--MLC technology Disclosed is a multilayer electronics packaging structure, especially for use in a multi chip module. By forming an overlap of signal conductors by the respective mesh conductors, an improved shielding effect is achieved and coupling between signal conduc... | 08/27/2002 |
| 6441479 | System-on-a-chip with multi-layered metallized through-hole interconnection The present invention is directed to a high-performance system on a clip which uses multi-layer wiring/insulation through-hole interconnections to provide short wiring and controlled low-impedance wiring including ground planes and power supply distributi... | 08/27/2002 |
| 6407341 | Conductive substructures of a multilayered laminate Conductive substructures of a multilayered laminate and associated methods of fabrication. The conductive substructures include a 0S1P substructure, a 0S3P substructure, and a 2S1P substructure, in accordance with the notation nSmP, wherein n and m are no... | 06/18/2002 |
| 6407907 | Multilayer ceramic capacitor A multilayer capacitor having a hexagonally-shaped capacitor body, a first internal electrode arranged therein, and a second internal electrode arranged below the first internal electrode separated by a ceramic layer. The capacitor body is provided with a... | 06/18/2002 |
| 6400573 | Multi-chip integrated circuit module A multi-chip integrated circuit module includes a supporting layer of laminate material over which a high-density interconnect structure is formed. The laminate layer includes a first upper laminate layer (10) having a hole (14) disposed therein for recei... | 06/04/2002 |
