Quotables
"It is my heart-warmed and world-embracing Christmas hope and aspiration that all of us, the high, the low, the rich, the poor, the admired, the despised, the loved, the hated, the civilized, the savage (every man and brother of us all throughout the whole earth), may eventually be gathered together in a heaven of everlasting rest and peace and bliss, except the inventor of the telephone. "
Mark Twain ; Christmas greetings, 1890
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| Number | Title | Issue Date |
| 7444253 | Air bridge structures and methods of making and using air bridge structures A probe card assembly, according to some embodiments of the invention, can comprise a tester interface configured to make electrical connections with a test controller, a plurality of electrically conductive probes disposed to contact terminals of an electronic devi... | 10/28/2008 |
| 7443039 | System for different bond pads in an integrated circuit package An integrated circuit package is provided with a substrate having first and second contact pads exposed through a passivation layer on the substrate. A first metallurgy layer is over the substrate. A second metallurgy layer is over the first metallurgy layer. A prot... | 10/28/2008 |
| 7443028 | Imaging module and method for forming the same An imaging module is formed by stacking: a first resin board; a second resin board having a first opening; a first electrically-conductive member electrically connecting the first resin board and the second resin board to each other; a printed circuit board having a... | 10/28/2008 |
| 7414309 | Encapsulated electronic part packaging structure An encapsulated electronic part packaging structure includes a step of mounting an electronic part having a connection terminal and a passivating film to cover the connection terminal, mounted on a body to direct the connection terminal upward. An insulating layer i... | 08/19/2008 |
| 7408262 | Semiconductor integrated circuit device A semiconductor integrated circuit device includes a semiconductor chip, a memory cell array arranged on the semiconductor chip and first and second decoder strings arranged along both ends of the memory cell array. The arrangement position of the first decoder stri... | 08/05/2008 |
| 7405476 | Asymmetric alignment of substrate interconnect to semiconductor die An apparatus includes a first semiconductor die and at least one further semiconductor die. A substrate is attached to the first die and the further die and has an electrical interconnect pattern that interconnects contacts on the first die with respective contacts ... | 07/29/2008 |
| 7405485 | Semiconductor device A semiconductor device provided with a first semiconductor chip having a first functional surface formed with a first functional element and a first rear surface, a second semiconductor chip having a second functional surface which is formed with a second functional... | 07/29/2008 |
| 7402442 | Physically highly secure multi-chip assembly A physically secure processing assembly is provided that includes dies mounted on a substrate so as to sandwich the electrical contacts of the dies between the dies and the substrate. The substrate is provided with substrate contacts and conductive pathways that are... | 07/22/2008 |
| 7393720 | Method for fabricating electrical interconnect structure A method for fabricating an electrical interconnect structure is adapted for a circuit board manufacturing process. The circuit board comprises a conductive substrate, which comprises a first conductive layer and a bump conductive layer. The bump conductive layer is... | 07/01/2008 |
| 7385293 | Copper alloy, fabrication method thereof, and sputtering target A Cu alloy for semiconductor interconnections contains at least one selected from the group consisting of 0.10 to 10 atomic percent of Sb, 0.010 to 1.0 atomic percent of Bi, and 0.01 to 3 atomic percent of Dy, with the balance being Cu and inevitable impurities. The... | 06/10/2008 |
| 7378340 | Method of manufacturing semiconductor device and semiconductor device The present invention provides a method of manufacturing a semiconductor device and a semiconductor device that allow use of interlayer and interconnect insulating films having a low dielectric constant in forming a dual damascene structure. A first insulating film,... | 05/27/2008 |
| 7341909 | Methods of forming semiconductor constructions The invention includes methods of forming semiconductor constructions in which electrically conductive structures are formed between bitlines to electrically connect with storage node contacts. The bitlines can be formed within trenches having faceted top portions. ... | 03/11/2008 |
| 7339277 | Semiconductor device having passive component and support substrate with electrodes and through electrodes passing through support substrate A capacitor comprises a first conducting film 12 formed on a substrate 10, a first dielectric film 14 formed on the first conducting film, a second conducting film 18 formed on the first dielectric film, a second dielectric film 22... | 03/04/2008 |
| 7335985 | Method and system for electrically coupling a chip to chip package A chip and a chip package can transmit information to each other by using a set of converters capable of communicating with each other through the emission and reception of electromagnetic signals. Both the chip and the chip package have at least one such converter ... | 02/26/2008 |
| 7327042 | Interconnection structure of electric conductive wirings Accumulating spaces for conductive particles are formed in gaps of wiring patterns for conductive wirings which are disposed on a surface of a supporting body. When interconnecting a pair of interconnection objects having the respective wiring patterns via an anisot... | 02/05/2008 |
| 7323773 | Semiconductor device There is disclosed a semiconductor device having first and second semiconductor chips. The first semiconductor chip has a memory circuit. The second semiconductor chip has a circuit controlling the memory circuit. The contour size of the semiconductor device is redu... | 01/29/2008 |
| 7321164 | Stack structure with semiconductor chip embedded in carrier A stack structure with semiconductor chips embedded in carriers comprises two carriers stacking together as a whole, at least two semiconductor chips having active surfaces with electrode pads and inactive surfaces corresponding thereto placed in the cavities of the... | 01/22/2008 |
| 7291906 | Stack package and fabricating method thereof Disclosed are a stack package and a fabricating method thereof using a ball grid array semiconductor package (hereinafter, referred to as “BGA PKG”). The stack package can easily electrically connect the stacked BGA PKGs with each other by simplifying a stack st... | 11/06/2007 |
| 7291929 | Semiconductor device and method of manufacturing thereof A connection method is disclosed for a high-performance semiconductor system. The connection method enables high-speed operation with low noise, so as to obtain reliable and excellent connection in a short TAT at low costs. Semiconductor chips and the interposer chi... | 11/06/2007 |
| 7235885 | Semiconductor device and method of manufacturing the same, circuit board and electronic device A semiconductor device includes a wiring board having a wiring pattern, a semiconductor chip that has an integrated circuit and is mounted on a first surface of the wiring board to electrically connect with the wiring pattern, a spacer that is disposed on a second s... | 06/26/2007 |
| 7205669 | Semiconductor device A semiconductor device that exhibits an enhanced inhibition to a generation of voids in an underfill resin for encapsulation supplied between a semiconductor chip and an electronic component, which are mutually coupled through bump electrodes. The semiconductor devi... | 04/17/2007 |
| 7193310 | Stacking system and method A chip stack comprising a flex circuit including a flex substrate having a first conductive pattern disposed thereon and a plurality of leads extending therefrom. Also included in the chip stack are at least two integrated circuit chip packages. The integrated circu... | 03/20/2007 |
| 7183644 | Integrated circuit package with improved power signal connection An integrated circuit (IC) package includes a substrate and an IC die mounted on a first side of the substrate. The IC package also includes a plurality of capacitors mounted on a second side of the substrate. The second side is opposite to the first side. The IC pa... | 02/27/2007 |
| 7160799 | Define via in dual damascene process The invention includes a process for manufacturing an integrated circuit, comprising providing a substrate comprising a dielectric layer over a conductive material, depositing a hardmask over the dielectric layer, applying a first photoresist over the hardmask and p... | 01/09/2007 |
| 7098541 | Interconnect method for directly connected stacked integrated circuits A method and related configuration for stacking and interconnecting multiple identical integrated circuit semiconductor die. A die designed in accordance with the present invention can be directly interconnected with other identical die by placing a second die on a ... | 08/29/2006 |
| 7091591 | Semiconductor device A semiconductor device formed by mutually connecting a first semiconductor chip with second and third semiconductor chips arranged side by side, with the active surface of the first chip faced to those of the second and third chip. Both the second and third semicond... | 08/15/2006 |
| 6864579 | Carrier with a metal area and at least one chip configured on the metal area A carrier has a metal area that is essentially composed of copper. A chip has a rear side metallization layer. A buffer layer, essentially composed of nickel and having a thickness of between 5 μm and 10 μm, is arranged on the metal area. The chip does not have a ... | 03/08/2005 |
| 6687842 | Off-chip signal routing between multiply-connected on-chip electronic elements via external multiconductor transmission line on a dielectric element A semiconductor chip is provided with a dielectric element having conductive features interconnecting electronic elements within the chip with one another. The conductive features replace internal conductors, and can provide enhanced signal propagation be... | 02/03/2004 |
| 6682981 | Stress controlled dielectric integrated circuit fabrication General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a sem... | 01/27/2004 |
| 6683662 | Semiconductor device and method for producing the same An interterminal anti-short-circuiting pattern is formed in an upper metal wire included in a connection terminal 3, for connecting to external driving LSI and the like, located on the projected portion of a bottom glass substrate 2. This pattern includes... | 01/27/2004 |
| 6683384 | Air isolated crossovers The specification describes integrated circuit air isolated crossover interconnections designed for flip chip multi-chip module interconnection technology. The crossovers are made using a crossover interconnection substrate separate from the interconnecti... | 01/27/2004 |
| 6645606 | Electrical device having metal pad bonded with metal wiring and manufacturing method thereof A substrate has a first surface and a second surface. A plurality of pads is formed on the first surfaces. Each pads has a Cu plating layer and an Au plating layer that is directly formed on the Cu plating layer. Al wiring or Au wiring is bonded with the ... | 11/11/2003 |
| 6586783 | Substrate for an electronic power circuit, and an electronic power module using such a substrate An electronic power circuit substrate including a wafer of electrically insulating material, wherein said wafer presents a face supporting one or more conductive tracks directly connected to one or more electronic power components, said conductive tracks ... | 07/01/2003 |
| 6584004 | Electronic circuit package An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and th... | 06/24/2003 |
| 6486551 | Wired board and method of producing the same A wired board comprises a plurality of bonding pads for connection to connecting terminals of an electronic part, and a plurality of external connection terminals for connection to connecting terminals of an external circuit board such as a motherboard. E... | 11/26/2002 |
| 6476332 | Conductor systems for thick film electronic circuits A thick film electronic circuit is disclosed. The circuit includes a substrate for supporting the circuit and a conductive trace for interconnecting a plurality of electronic devices dispersed on the thick film electronic circuit. The conductive trace inc... | 11/05/2002 |
| 6407340 | Electric conductor with a surface structure in the form of flanges and etched grooves An electronics device comprising a carrier, such as a printed circuit board, a substrate or a chip, and an electric conductor on a surface of the carrier. The surface of the conductor (2) facing away from the carrier has a surface structure (3, 4; 6, 7) i... | 06/18/2002 |
| 6365975 | Chip with internal signal routing in external element A semiconductor chip is provided with a dielectric element having conductive features interconnecting electronic elements within the chip with one another. The conductive features replace internal conductors, and can provide enhanced signal propagation be... | 04/02/2002 |
| 6346744 | Integrated RF M×N switch matrix A switch matrix comprising a mulitlayer ceramic circuit board having a M×N array of N×N switch modules. Specifically, the ceramic circuit board has a M×N array of mounting sites for accepting individual N×N switch modules. The ceramic circuit board co... | 02/12/2002 |
| 6323931 | LCD with external circuit having anti-short-circuit pattern and particular structure An interterminal anti-short-circuiting pattern is formed in an upper metal wire included in a connection terminal 3, for connecting to external driving LSI and the like, located on the projected portion of a bottom glass substrate 2. This pattern includes... | 11/27/2001 |
