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| Number | Title | Issue Date |
| 7411259 | Wiring material and a semiconductor device having a wiring using the material, and the manufacturing method thereof An object of the present invention is to realize a semiconductor device having a high TFT characteristic. In manufacturing an active matrix display device, electric resistivity of the electrode material is kept low by preventing penetration of oxygen ion into the el... | 08/12/2008 |
| 7405485 | Semiconductor device A semiconductor device provided with a first semiconductor chip having a first functional surface formed with a first functional element and a first rear surface, a second semiconductor chip having a second functional surface which is formed with a second functional... | 07/29/2008 |
| 7396762 | Interconnect structures with linear repair layers and methods for forming such interconnection structures Interconnect structures that include a conformal liner repair layer bridging breaches in a liner formed on roughened dielectric material in an insulating layer and methods of forming such interconnect structures. The conformal liner repair layer is formed of a condu... | 07/08/2008 |
| 7378340 | Method of manufacturing semiconductor device and semiconductor device The present invention provides a method of manufacturing a semiconductor device and a semiconductor device that allow use of interlayer and interconnect insulating films having a low dielectric constant in forming a dual damascene structure. A first insulating film,... | 05/27/2008 |
| 7078331 | Method of forming redistribution bump and semiconductor chip and mount structure fabricated using the same Provided are a method of forming a bump whose upper surface is substantially flat and whose area can be enlarged in a uniform pad pitch to simplify mounting a liquid crystal display drive IC (LDI) and a semiconductor chip and a mount structure using the method to mi... | 07/18/2006 |
| 6696746 | Buried conductors Buried conductors within semiconductor devices and structures, and methods for forming such conductors, are disclosed. In one embodiment of the invention, a semiconductor structure includes a substrate and a plurality of conductive elements buried within ... | 02/24/2004 |
| 6696732 | Semiconductor device having S/D to S/D connection and isolation region between two semiconductor elements A plurality of MOS type FET devices 14 and 16 are provided on a semiconductor substrate 12. A lower interlayer insulating film 20 is provided thereon. Each of through holes 22, which extends from each of gate electrodes 14c of the plural FET devices via s... | 02/24/2004 |
| 6693025 | Local interconnect structures for integrated circuits and methods for making the same A method for making a flexible metal silicide local interconnect structure. The method includes forming an amorphous or polycrystalline silicon layer on a substrate including at least one gate structure, forming a layer of silicon nitride over the silicon... | 02/17/2004 |
| 6661048 | Semiconductor memory device having self-aligned wiring conductor According to the present invention, an overlay margin is secured for matching a wiring electrode 11 with a storage electrode 15 of a capacitor at their point of contact and the required area for a memory cell can be decreased by placing the plug electrode... | 12/09/2003 |
| 6656825 | Semiconductor device having an improved local interconnect structure and a method for forming such a device In a semiconductor device including one or more semiconductor containing lines, such as gate electrodes of transistor elements, and/or active areas, sidewall spacer elements of the one or more semiconductor containing lines include a conductive layer that... | 12/02/2003 |
| 6627528 | Semiconductor device and its manufacturing process Gate electrodes in an inverter section and a transfer section are formed only on element areas, and connected to each other by means of local interconnection layers. As a result, a memory cell of a very small size but a large capacity can be formed withou... | 09/30/2003 |
| 6593632 | Interconnect methodology employing a low dielectric constant etch stop layer The capacitance between the gate of a transistor and local interconnect is reduced employing SiC as an etch stop layer. Embodiments include depositing a SiC etch stop layer having a thickness of about 500-1000 Å and a dielectric constant of less than abo... | 07/15/2003 |
| 6593631 | Method of fabricating semiconductor device A method of fabricating a semiconductor device includes the steps of: forming a well of first conductivity type and well of second conductivity type in a substrate; forming a field oxide layer and gate oxide layer on the substrate; forming first and secon... | 07/15/2003 |
| 6576510 | Method of producing a semiconductor memory device using a self-alignment process According to the present invention, an overlay margin is secured for matching a wiring electrode 11 with a storage electrode 15 of a capacitor at their point of contact and the required area for a memory cell can be decreased by placing the plug electrode... | 06/10/2003 |
| 6555478 | Stacked local interconnect structure and method of fabricating same A method of forming stacked local interconnects that do not extend into higher levels within a multilevel IC device for economizing space available within the IC device and increasing design flexibility. In one embodiment, the method of the present invent... | 04/29/2003 |
| 6548871 | Semiconductor device achieving reduced wiring length and reduced wiring delay by forming first layer wiring and gate upper electrode in same wire layer Two source/drain regions (20) belonging to separate elements which are adjacent to each other are connected through a metal layer (14) having the same height as a height of a metal layer (10) forming a part of a gate electrode. In a manufacturing process,... | 04/15/2003 |
| 6544881 | Stacked local interconnect structure and method of fabricating same A method of forming stacked local interconnects that do not extend into higher levels within a multilevel IC device, thereby economizing space available within the IC device and increasing design flexibility. In a first embodiment, the method of the prese... | 04/08/2003 |
| 6503787 | Device and method for forming semiconductor interconnections in an integrated circuit substrate The present invention provides a semiconductor device, formed on a semiconductor wafer, comprising a tub, first and second active areas, and an interconnect. In one aspect of the present invention, the tub is formed in the substrate of the semiconductor w... | 01/07/2003 |
| 6498088 | Stacked local interconnect structure and method of fabricating same The present invention minimizes or eliminates the disadvantages associated with multilevel interconnect structures by providing a method of forming stacked local interconnects that do not extend into higher levels within a multilevel IC device, thereby ec... | 12/24/2002 |
| 6486056 | Process for making integrated circuit structure with thin dielectric between at least local interconnect level and first metal interconnect level An integrated circuit structure is provided with a local interconnect layer and a first metal interconnect layer which are both capable of bridging over underlying conductive regions. The structure comprises a first dielectric layer formed to a height or ... | 11/26/2002 |
| 6482689 | Stacked local interconnect structure and method of fabricating same A method of forming stacked local interconnects that do not extend into higher levels within a multilevel IC device for economizing space available within the IC device and increasing design flexibility. In one embodiment, the method of the present invent... | 11/19/2002 |
| 6448656 | System including a memory device having a semiconductor connection with a top surface having an enlarged recess A method of forming a connection is comprised of the steps of depositing a lower conductor. A dielectric layer is deposited on the lower conductor, with the dielectric layer having a lower surface adjacent to the lower conductor, and having an upper surfa... | 09/10/2002 |
| 6429124 | Local interconnect structures for integrated circuits and methods for making the same A method for making a flexible metal silicide local interconnect structure. The method includes forming an amorphous or polycrystalline silicon layer on a substrate including at least one gate structure, forming a layer of silicon nitride over the silicon... | 08/06/2002 |
| 6429526 | Method for forming a semiconductor connection with a top surface having an enlarged recess A method of forming a connection is comprised of the steps of depositing a lower conductor. A dielectric layer is deposited on the lower conductor, with the dielectric layer having a lower surface adjacent to the lower conductor, and having an upper surfa... | 08/06/2002 |
| 6426287 | Method for forming a semiconductor connection with a top surface having an enlarged recess A method of forming a connection is comprised of the steps of depositing a lower conductor. A dielectric layer is deposited on the lower conductor, with the dielectric layer having a lower surface adjacent to the lower conductor, and having an upper surfa... | 07/30/2002 |
| 6426558 | Metallurgy for semiconductor devices A method and structure is described which improves the manufacturability of integrated circuit interconnect and stud contacts in contact with semiconductor substrates and upper levels of metallization. The monolithic structure is formed from a thick layer... | 07/30/2002 |
| 6400024 | Method of providing a vertical interconnect between thin film microelectronic devices A simple and reliable method of providing a vertical interconnect between thin-film microelectronic devices is provided. In said method, a tool tip is used to make a notch in a vertical interconnect area of two organic electrically conducting areas separa... | 06/04/2002 |
| 6383924 | Method of forming buried conductor patterns by surface transformation of empty spaces in solid state materials A plurality of buried conductors and/or buried plate patterns formed within a monocrystalline substrate is disclosed. A plurality of empty-spaced buried patterns are formed by drilling holes in the monocrystalline substrate and annealing the monocrystalli... | 05/07/2002 |
| 6380023 | Methods of forming contacts, methods of contacting lines, methods of operating integrated circuitry, and integrated circuits Methods of forming contacts, methods of contacting lines, methods of operating integrated circuitry, and related integrated circuitry constructions are described. In one embodiment, a plurality of conductive lines are formed over a substrate and diffusion... | 04/30/2002 |
| 6297156 | Method for enhanced filling of high aspect ratio dual damascene structures An integrated circuit alloy is described which reduces the alloy melting temperature for improved coverage of high aspect ratio features with a reduced deposition pressure. The alloy is used to fabricate metal contacts and interconnects in integrated circ... | 10/02/2001 |
| 6277731 | Method for forming a semiconductor connection with a top surface having an enlarged recess A method of forming a connection is comprised of the steps of depositing a lower conductor. A dielectric layer is deposited on the lower conductor, with the dielectric layer having a lower surface adjacent to the lower conductor, and having an upper surfa... | 08/21/2001 |
| 6261908 | Buried local interconnect A method of fabricating a buried local interconnect in a substrate and an integrated circuit incorporating the same are provided. The method includes the steps forming a trench in the substrate and forming a first insulating layer in the trench. A conduct... | 07/17/2001 |
| 6258683 | Local interconnection arrangement with reduced junction leakage and method of forming same A method and arrangement for forming a local interconnect without etching completely through a junction and causing device shorts introduces an additional ion implantation step following the etching of the local interconnect opening into the substrate. Th... | 07/10/2001 |
| 6258647 | Method of fabricating semiconductor device A method of fabricating a semiconductor device includes the steps of: forming a well of first conductivity type and well of second conductivity type in a substrate; forming a field oxide layer and gate oxide layer on the substrate; forming first and secon... | 07/10/2001 |
| 6255701 | Semiconductor device containing local interconnection and method of manufacturing the same A semiconductor device has a local interconnecting part (20) for electrically connecting a silicon-containing first layer (12) and silicon-containing second layer (16). The local interconnecting part has a first metal silicide layer (22a) formed in a self... | 07/03/2001 |
| 6239491 | Integrated circuit structure with thin dielectric between at least local interconnect level and first metal interconnect level, and process for making same An integrated circuit structure is provided with a local interconnect layer and a first metal interconnect layer which are both capable of bridging over underlying conductive regions. The structure comprises a first dielectric layer formed to a height or ... | 05/29/2001 |
| 6215158 | Device and method for forming semiconductor interconnections in an integrated circuit substrate The present invention provides a semiconductor device, formed on a semiconductor wafer, comprising a tub, first and second active areas, and an interconnect. In one aspect of the present invention, the tub is formed in the substrate of the semiconductor w... | 04/10/2001 |
| 6211054 | Method of forming a conductive line and method of forming a local interconnect The invention includes methods of forming conductive lines, such as local interconnects. In one implementation, a method of forming a conductive line includes depositing a first layer comprising polymer silicon on a substrate. A metal layer is deposited a... | 04/03/2001 |
| 6201303 | Method of forming a local interconnect with improved etch selectivity of silicon dioxide/silicide A method and arrangement for forming a local interconnect without weakening the field edge or disconnecting the diffusion region at the field edge introduces additional nitrogen by ion implantation into a nitrogen-containing etch stop layer (e.g., SiON) t... | 03/13/2001 |
| 6136633 | Trench-free buried contact for locos isolation A new method of forming an improved buried contact junction is described. A gate oxide layer is provided over the surface of a semiconductor substrate. A first polysilicon layer is deposited over the gate oxide layer. A photoresist mask is formed over the... | 10/24/2000 |
