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| Number | Title | Issue Date |
| 7443032 | Memory device with chemical vapor deposition of titanium for titanium silicide contacts A titanium layer is formed on a substrate with chemical vapor deposition (CVD). First, a seed layer is formed on the substrate by combining a first precursor with a reducing agent by CVD. Then, the titanium layer is formed on the substrate by combining a second prec... | 10/28/2008 |
| 7414315 | Damascene structure with high moisture-resistant oxide and method for making the same A semiconductor device includes a substrate, an inter-metal dielectric (IMD) layer over the substrate, and either a nitrogen-containing tetraethoxysilane (TEOS) oxide layer or an oxygen-rich TEOS oxide layer over the IMD layer. The molecular ratio of oxygen in the o... | 08/19/2008 |
| 7402883 | Back end of the line structures with liner and noble metal layer A back end of the line (BEOL) structure of a semiconductor device is presented. In one embodiment, the structure may include a first liner layer disposed on an intermediate interconnect structure, the intermediate interconnect structure having an opening disposed be... | 07/22/2008 |
| 7368804 | Method and apparatus of stress relief in semiconductor structures A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad a... | 05/06/2008 |
| 7361991 | Closed air gap interconnect structure A closed air gap interconnect structure is described. The structure includes discrete regions of a permanent support dielectric under the interconnect lines so that the lines are substantially surrounded by air except for the discrete regions of the support dielectr... | 04/22/2008 |
| 7338895 | Method for dual damascene integration of ultra low dielectric constant porous materials A dual damascene interconnect structure having a patterned multilayer of spun-on dielectrics on a substrate is provided. The structure includes: a patterned multilayer of spun-on dielectrics on a substrate, including: a cap layer; a first non-porous via level low-k ... | 03/04/2008 |
| 7335585 | Method for preventing the formation of a void in a bottom anti-reflective coating filling a via hole A method for manufacturing a semiconductor device which, on performing a via first Dual Damascene process, inhibits or prevents the formation of a void in a bottom anti-reflective coating filling a via hole. The method typically includes the steps of forming a botto... | 02/26/2008 |
| 7301241 | Semiconductor device for preventing defective filling of interconnection and cracking of insulating film The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 | 11/27/2007 |
| 7291923 | Tapered signal lines In an integrated circuit, a layer including a plurality of conductive wires is described. A first wire, having sidewalls, is tapered from a proximal end which has a first width to a distal end which has a second width, to reduce width from the first width to the sec... | 11/06/2007 |
| 7256146 | Method of forming a ceramic diffusion barrier layer The present invention comprises an interconnect structure including a metal, interlayer dielectric and a ceramic diffusion barrier formed therebetween, where the ceramic diffusion barrier has a composition SivNwCxOyHz... | 08/14/2007 |
| 7224064 | Semiconductor device having conductive interconnections and porous and nonporous insulating portions A semiconductor device and manufacturing method, wherein the semiconductor device has a semiconductor substrate on which a plurality of elements constituting a logic type device have been formed; a first interlayer insulating film on the semiconductor substrate; a p... | 05/29/2007 |
| 7208427 | Precursor compositions and processes for MOCVD of barrier materials in semiconductor manufacturing Metalorganic precursors of the formula: (R1R2N)a−bMXb wherein: M is the precursor metal center, selected from the group of Ta, Ti, W, Nb, Si, Al and B; a is a number equal to the valence of M; 1≦bâ‰... | 04/24/2007 |
| 7180191 | Semiconductor device and method of manufacturing a semiconductor device A semiconductor device 200 comprises a SiCN film 202 formed on a semiconductor substrate (not shown), a first SiOC film 204 formed thereon, a SiCN film 208 formed thereon, a second SiOC film 210 formed thereon, a SiO2 fi... | 02/20/2007 |
| 7164191 | Low relative permittivity SiOfilm including a porous material for use with a semiconductor device A low relative permittivity SiOx film excellent in heat resistance without using an alkali metal, fluorine, etc., a method for modifying an SiOx film to accomplish a further reduction of the relative permittivity of the low relative permittivit... | 01/16/2007 |
| 7157792 | Forming a substantially planar upper surface at the outer edge of a semiconductor topography A method is provided for processing a semiconductor topography such that its upper surface is substantially planar, particularly including a region adjacent to an outer edge of a semiconductor topography. The method may include preferentially removing a portion of a... | 01/02/2007 |
| 7148535 | Zero capacitance bondpad utilizing active negative capacitance The present invention is an apparatus and system for reducing bondpad capacitance of an integrated circuit. Circuitry of the present invention may produce a negative capacitance approximately equal in magnitude to the capacitance associated with the bondpad and ther... | 12/12/2006 |
| 7115501 | Method for fabricating an integrated circuit device with through-plating elements and terminal units A method for fabricating an integrated circuit device, an electrically conductive substrate being provided, an insulation layer being deposited on the substrate, the insulation layer being etched in structures, a contact-making layer being deposited on the patterned... | 10/03/2006 |
| 7105928 | Copper wiring with high temperature superconductor (HTS) layer Semiconductor devices and methods of forming the semiconductor devices using an HTS (High Temperature Superconductor) layer in combination with a typical diffusion layer between the dielectric material and the copper (or other metal) conductive wiring. The HTS layer... | 09/12/2006 |
| 7091618 | Semiconductor device and method of manufacturing the same An insulating film having dielectric constant not greater than 2.7 is provided above a semiconductor substrate. A via comprises a conductive material, which is provided in a via hole formed in the insulating film. A first interconnection comprises a conductive mater... | 08/15/2006 |
| 7088003 | Structures and methods for integration of ultralow-k dielectrics with improved reliability An improved back end of the line (BEOL) interconnect structure comprising an ultralow k (ULK) dielectric is provided. The structure may be of the single or dual damascene type and comprises a dense thin dielectric layer (TDL) between a metal barrier layer and the UL... | 08/08/2006 |
| 6924346 | Etch-stop resins Silicone resins comprising 5 to 50 mole % of (PhSiO3-x)/2(OH)x) units and 50 to 95 mole % (HSiO(3-x)/2(OH)x), where Ph is a phenyl group, x has a value of 0, 1 or 2 and wherein the cured silicone resin has a critical surfa... | 08/02/2005 |
| 6696315 | Semiconductor device configuration with cavities of submicrometer dimensions and method of fabricating structured cavities Cavities of submicron dimension are in a cavity layer of a semiconductor device. For that purpose, processing material is deposited on ridges of a working layer that is structured from ridges and trenches. The processing material is polymerized and the po... | 02/24/2004 |
| 6690091 | Damascene structure with reduced capacitance using a boron carbon nitride passivation layer, etch stop layer, and/or cap layer A damascene structure with reduced capacitance dielectric stacking comprise a passivation, a first dielectric, an etch stop, a second dielectric and a cap layer over a first conductive layer formed on a semiconductor. The passivation, the etch stop, and t... | 02/10/2004 |
| 6685983 | Defect-free dielectric coatings and preparation thereof using polymeric nitrogenous porogens Defect-free dielectric coatings comprised of porous polymeric matrices are prepared using nitrogen-containing polymers as pore-generating agents. The dielectric coatings are useful in a number of contexts, including the manufacture of electronic devices s... | 02/03/2004 |
| 6680541 | Semiconductor device and process for producing the same An intermetal insulating film containing at least silicon atoms, oxygen atoms and carbon atoms with the number ratio of oxygen atom to silicon atom being 1.5 or more and the number ratio of carbon atom to silicon atom being 1 to 2, and having a film thick... | 01/20/2004 |
| 6674168 | Single and multilevel rework A method of reworking BEOL (back end of a processing line) metallization levels of damascene metallurgy comprises forming a plurality of BEOL metallization levels over a substrate, forming line and via portions in the BEOL metallization levels, selectivel... | 01/06/2004 |
| 6674146 | Composite dielectric layers An apparatus including a contact point on a substrate; a first dielectric layer comprising a material having a dielectric constant less than five formed on the contact point, and a different second dielectric layer formed on the substrate and separated fr... | 01/06/2004 |
| 6670285 | Nitrogen-containing polymers as porogens in the preparation of highly porous, low dielectric constant materials Dielectric compositions comprised of porous polymeric matrices are prepared using nitrogen-containing polymers as pore-generating agents. The compositions are useful in the manufacture of electronic devices such as integrated circuit devices and integrate... | 12/30/2003 |
| 6670715 | Bilayer silicon carbide based barrier A bilayer SiC-based barrier is formed over a metallic wiring layer and a first dielectric layer. The bilayer SiC-based barrier consists of a nitrogen-doped SiC bottom layer and an oxygen-doped SiC top layer. The nitrogen-doped SiC bottom layer has a minim... | 12/30/2003 |
| 6670709 | Semiconductor device and method of manufacturing the same A first HSQ film composed of a Si--O-based film with a low dielectric constant is formed on a first wiring via a protective insulation film, and the surface of this first HSQ film is reformed to form a first SRO layer. Then, a second HSQ film is formed on... | 12/30/2003 |
| 6670284 | Method of decontaminating process chambers, methods of reducing defects in anti-reflective coatings, and resulting semiconductor structures A method for fabricating a substantially smooth-surfaced anti-reflective coating on a semiconductor device structure including generating a plasma from an inert gas in a process chamber in which the anti-reflective coating is to be deposited. The anti-ref... | 12/30/2003 |
| 6670022 | Nanoporous dielectric films with graded density and process for making such films The present invention relates to nanoporous dielectric films and to a process for their manufacture. A substrate having a plurality of raised lines on its surface is provided with a relatively high porosity, low dielectric constant, silicon containing pol... | 12/30/2003 |
| 6670710 | Semiconductor device having multi-layered wiring A semiconductor device is provided with a first insulating film, a first wiring layer formed in the first insulating film, a second insulating film formed above the first wiring layer and the first insulating film, the second insulating film including a l... | 12/30/2003 |
| 6667533 | Triple damascene fuse Disclosed is a conductive fuse for a semiconductor device, comprising: a pair of contact portions integrally connected to a fusible portion by connecting portions; the contact portions thicker than the connecting portions and the connecting portions thick... | 12/23/2003 |
| 6667236 | Method of manufacturing a two layer liner for dual damascene vias The invention relates to a semiconductor device comprising a substrate (1) comprising for instance silicon with thereon a layer (2, 4) comprising at least organic material which contains a passage (6, 8) to the substrate (1). The passage (6,8) has walls (... | 12/23/2003 |
| 6664192 | Method for bottomless deposition of barrier layers in integrated circuit metallization schemes Methods are disclosed for selective deposition on desired materials. In particular, barrier materials are selectively formed on insulating surfaces, as compared to conductive surfaces. In the context of contact formation and trench fill, particularly dama... | 12/16/2003 |
| 6661094 | Semiconductor device having a dual damascene interconnect spaced from a support structure A semiconductor device and an improved method for making it are described. The semiconductor device comprises a dual damascene interconnect that includes a conductive line. The device further includes a support structure that is spaced from the conductive... | 12/09/2003 |
| 6660618 | Reverse mask and oxide layer deposition for reduction of vertical capacitance variation in multi-layer metallization systems Excessive variation in vertical (i.e., inter-level) capacitance of multi-level metallization semiconductor devices resulting in racing of clock skew circuitry of finished devices, and over-etching of borderless vias leading to inter-level short-circuits, ... | 12/09/2003 |
| 6657284 | Graded dielectric layer and method for fabrication thereof Within a method for forming a dielectric layer, there is first provided a substrate. There is then formed over the substrate a dielectric layer, wherein the dielectric layer is formed from a dielectric material comprising silicon, carbon and nitrogen. Pre... | 12/02/2003 |
| 6657310 | Top layers of metal for high performance IC's A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or pol... | 12/02/2003 |
