Bizarre Patents
Dining Table Having Integral Dishwasher
A space-saving dishwasher, which may be installed within a counter top or table, having a dish-carrying rack that is vertically shiftable through the open top of the dishwasher for facilitating loading and unloading of the dishes.
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| Number | Title | Issue Date |
| 7384863 | Semiconductor device and method for manufacturing the same In a disclosed COC type semiconductor device, a bump electrode (21) of a second semiconductor chip (2) is joined to a first semiconductor chip (1) having a bump electrode (11) formed thereon. The bump electrodes (11) and (21... | 06/10/2008 |
| 7276796 | Formation of oxidation-resistant seed layer for interconnect applications An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the surface oxidation problem of plating a conductive material onto a noble metal seed layer are provided. In accordance with the present inv... | 10/02/2007 |
| 6664192 | Method for bottomless deposition of barrier layers in integrated circuit metallization schemes Methods are disclosed for selective deposition on desired materials. In particular, barrier materials are selectively formed on insulating surfaces, as compared to conductive surfaces. In the context of contact formation and trench fill, particularly dama... | 12/16/2003 |
| 6589414 | Nitride layer forming methods Nitride layer formation includes a method wherein a material is electrodeposited on a substrate and converted, at least in part, to a layer comprising nitrogen and the electrodeposited material. The electrodepositing may occur substantially selective on a... | 07/08/2003 |
| 6583022 | Methods of forming roughened layers of platinum and methods of forming capacitors In one aspect, the invention includes a method of forming a roughened layer of platinum, comprising: a) providing a substrate within a reaction chamber; b) flowing an oxidizing gas into the reaction chamber; c) flowing a platinum precursor into the reacti... | 06/24/2003 |
| 6579785 | Method of making multi-level wiring in a semiconductor device A method of manufacturing a semiconductor device, which comprises the steps of forming an intermediate layer on an insulating layer, forming a groove in the intermediate layer and the insulating layer, forming a first barrier layer on the intermediate lay... | 06/17/2003 |
| 6552432 | Mask on a polymer having an opening width less than that of the opening in the polymer A typical integrated circuit interconnects millions of microscopic transistors and resistors with aluminum wires buried in silicon-dioxide insulation. Yet, aluminum wires and silicon-dioxide insulation are a less attractive combination than gold, silver, ... | 04/22/2003 |
| 6541859 | Methods and structures for silver interconnections in integrated circuits A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Making the aluminum wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, ... | 04/01/2003 |
| 6515365 | Semiconductor device having a ground plane and manufacturing method thereof A semiconductor device includes at least first and second lower layer wirings provided on a surface of an insulator on a semiconductor substrate, a first interlayer film provided on the insulator to cover surfaces of the first and second lower layer wirin... | 02/04/2003 |
| 6486514 | Wiring line assembly for thin film transistor array substrate and a method for fabricating the same According to one aspect of the present invention, the thin film transistor array substrate basically includes a gate line assembly based on an Ag alloy. The Ag alloy comprises Ag and at least one of alloy elements and the alloy elements each bearing a low... | 11/26/2002 |
| 6440230 | Nitride layer forming method Nitride layer formation includes a method where a material is electrodeposited on a substrate and converted, at least in part, to a layer comprising nitrogen and the electrodeposited material. The electrodepositing may occur substantially selective on a c... | 08/27/2002 |
| 6433431 | Coating of copper and silver air bridge structures An improved electrical interconnect for an integrated circuit and methods for providing the same are disclosed. The interconnect includes an air bridge extending through an air space so as to reduce the capacitance of the interconnect. The air bridge is s... | 08/13/2002 |
| 6410985 | Silver metallization by damascene method Silver interconnects are formed by etching deep grooves into an insulating layer over the contact regions, exposing portions of the contact regions and defining the interconnects. The grooves are etched with a truncated V- or U-shape, wider at the top tha... | 06/25/2002 |
| 6338973 | Semiconductor device and method of fabrication A mass production process for semiconductor circuits and modules using a combination of thin film platinum metallization dielectric masking, and three-dimensional laser ablation, in conjunction with a solder combinations and melting temperatures. These co... | 01/15/2002 |
| 6297146 | Low resistivity semiconductor barrier layer manufacturing method A semiconductor, and manufacturing method therefor, is provided with a barrier/adhesion layer, having cobalt, nickel, or palladium for semiconductors having conductive materials of copper, silver or gold. The barrier/adhesion layer can be alloyed with bet... | 10/02/2001 |
| 6291305 | Method for implementing resistance, capacitance and/or inductance in an integrated circuit On-chip resistance, capacitance and/or inductance is implemented in an integrated circuit in vertical configurations using stacked vias and medullization layers within the integrated circuit. Column shaped openings or vias are formed within the integrated... | 09/18/2001 |
| 6281161 | Platinum-containing materials and catalysts In one aspect, the invention includes a method of forming a roughened layer of platinum, comprising: a) providing a substrate within a reaction chamber; b) flowing an oxidizing gas into the reaction chamber; c) flowing a platinum precursor into the reacti... | 08/28/2001 |
| 6255733 | Metal-alloy interconnections for integrated circuits Novel metal-alloy interconnections for integrated circuits. The metalalloy interconnections of the present invention comprise a substantial portion of either copper or silver alloyed with a small amount of an additive having a low residual resistivity and... | 07/03/2001 |
| 6239021 | Dual barrier and conductor deposition in a dual damascene process for semiconductors An integrated circuit and a method for manufacturing therefor is provided in which a partial dual damascene deposition is performed to place a barrier, seed, and conductive layer in most of a via between two interconnect channels and then capping the via ... | 05/29/2001 |
| 6221751 | Wafer fabrication of die-bottom contacts for electronic devices A packaging technique for electronic devices includes wafer fabrication of contacts on the bottom surface of the substrate underneath the active circuit. Inherently reliable contacts suitable for a variety of devices can be formed, via a simple fabricatio... | 04/24/2001 |
| 6211049 | Forming submicron integrated-circuit wiring from gold, silver, copper, and other metals A typical integrated circuit interconnects millions of microscopic transistors and resistors with aluminum wires buried in silicon-dioxide insulation. Yet, aluminum wires and silicon-dioxide insulation are a less attractive combination than gold, silver, ... | 04/03/2001 |
| 6208016 | Forming submicron integrated-circuit wiring from gold, silver, copper and other metals A typical integrated circuit interconnects millions of microscopic transistors and resistors with aluminum wires buried in silicon-dioxide insulation. Yet, aluminum wires and silicon-dioxide insulation are a less attractive combination than gold, silver, ... | 03/27/2001 |
| 6208032 | Semiconductor device and fabrication method thereof A semiconductor device having an inter-layer insulation film that allows a refractory metal to be easily etched and that well covers high side walls of a gold plate and a fabrication method thereof are disclosed. The semiconductor device comprises a semic... | 03/27/2001 |
| 6147404 | Dual barrier and conductor deposition in a dual damascene process for semiconductors An integrated circuit and a method for manufacturing therefor is provided in which a partial dual damascene deposition is performed to place a barrier, seed, and conductive layer in most of a via between two interconnect channels and then capping the via ... | 11/14/2000 |
| 6144096 | Low resistivity semiconductor barrier layers and manufacturing method therefor A semiconductor, and manufacturing method therefor, is provided with a barrier/adhesion layer, having cobalt, nickel, or palladium for semiconductors having conductive materials of copper, silver or gold. The barrier/adhesion layer can be alloyed with bet... | 11/07/2000 |
| 6143655 | Methods and structures for silver interconnections in integrated circuits A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Making the aluminum wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, ... | 11/07/2000 |
| 6121685 | Metal-alloy interconnections for integrated circuits Novel metal-alloy interconnections for integrated circuits. The metal-alloy interconnections of the present invention comprise a substantial portion of either copper or silver alloyed with a small amount of an additive having a low residual resistivity an... | 09/19/2000 |
| 6100194 | Silver metallization by damascene method Silver interconnects are formed by etching deep grooves into an insulating layer over the contact regions, exposing portions of the contact regions and defining the interconnects. The grooves are etched with a truncated V- or U-shape, wider at the top tha... | 08/08/2000 |
| 6100176 | Methods and structures for gold interconnections in integrated circuits A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Making the aluminum wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, ... | 08/08/2000 |
| 6090699 | Method of making a semiconductor device A method of making a semiconductor device includes a semiconductor substrate in which a semiconductor element is formed, an interlayer insulating film formed on the semiconductor substrate, an insulating barrier layer, formed on the interlayer insulating ... | 07/18/2000 |
| 6049132 | Multiple metallization structure for a reflection type liquid crystal display In a semiconductor chip for Si chip based liquid crystal having insulating films and interconnection layers formed on a semiconductor substrate, a thin interconnection layer made of TiN/Ti having strong erosion resistance is formed on an uppermost interla... | 04/11/2000 |
| 5990559 | Circuitry comprising roughened platinum layers, platinum-containing materials, capacitors comprising roughened platinum layers, methods forming roughened layers of platinum, and methods of forming capacitors In one aspect, the invention includes a method of forming a roughened layer of platinum, comprising: a) providing a substrate within a reaction chamber; b) flowing an oxidizing gas into the reaction chamber; c) flowing a platinum precursor into the reacti... | 11/23/1999 |
| 5973342 | Semiconductor device having an iridium electrode An iridium layer (16) is formed on an inter-layer insulation film (12) and in an opening (14). The iridium layer (16) is constituted with a part to be a lower electrode (16a) of a capacitor and a part to be a wiring (16b) for coming into contact with a dr... | 10/26/1999 |
| 5965934 | Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance ICS The interconnects in a semiconductor device contacting metal lines comprise a low resistance metal, such as copper, gold, silver, or platinum, and are separated by a material having a low dielectric constant, such as benzocyclobutene or a derivative there... | 10/12/1999 |
| 5920794 | Electromigration resistant metallization process microcircuit interconnections with RF-reactively sputtered titanium tungsten and gold Two metallization schemes of PtSi/TiW/TiW(N)/Au (Type I) and PtSi/TiW/TiW(N)/TiW/Au (Type II) and associated process are described for microcircuit interconnections. The metallization schemes and process are capable of IC-interconnections with a metal-pit... | 07/06/1999 |
| 5920121 | Methods and structures for gold interconnections in integrated circuits A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Making the aluminum wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, ... | 07/06/1999 |
| 5910687 | Wafer fabrication of die-bottom contacts for electronic devices A packaging technique for electronic devices includes wafer fabrication of contacts on the bottom surface of the substrate underneath the active circuit. Inherently reliable contacts suitable for a variety of devices can be formed, via a simple fabricatio... | 06/08/1999 |
| 5897370 | High aspect ratio low resistivity lines/vias by surface diffusion A method of filling high aspect ratio vias and lines on the upper surface of a substrate prevents voids from being formed therein. The method comprises the steps of filling the lines and vias by surface diffusion at room temperature and at a pressure of 1... | 04/27/1999 |
| 5877084 | Method for fabricating high aspect ratio low resistivity lines/vias by surface reaction A structure and method for fabricating circuits which use field effect transistors (FETs), bipolar transistors, or BiCMOS (combined Bipolar/Complementary Metal Oxide Silicon structures), uses low temperature germanium gas flow to affect metals and alloys ... | 03/02/1999 |
| 5856026 | High aspect ratio low resistivity lines/vias by surface diffusion A structure and method for fabricating circuits which use field effect transistors (FETs), bipolar transistors, or BiCMOS (combined Bipolar/Complementary Metal Oxide Silicon structures), uses low temperature germanium gas flow to affect metals and alloys ... | 01/05/1999 |
