Class 257/E23.161 - Principal metal being copper (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E23.157. This subclass
No. of patents: 71
Last issue date: 10/28/2008

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Number	Title	Issue Date
7443032	Memory device with chemical vapor deposition of titanium for titanium silicide contacts A titanium layer is formed on a substrate with chemical vapor deposition (CVD). First, a seed layer is formed on the substrate by combining a first precursor with a reducing agent by CVD. Then, the titanium layer is formed on the substrate by combining a second prec...	10/28/2008
7423347	In-situ deposition for cu hillock suppression A semiconductor interconnect structure having reduced hillock formation and a method for forming the same are provided. The semiconductor interconnect structure includes a conductor formed in a dielectric layer. The conductor includes at least three sub-layers, wher...	09/09/2008
7422977	Copper adhesion improvement device and method A semiconductor device, in which a semiconductor integrated circuit having a multi-level interconnection structure is formed, according to an embodiment of the present invention, comprises a copper wiring and an insulating layer formed on a top surface of the copper...	09/09/2008
7413983	Plating method including pretreatment of a surface of a base metal The present invention provides a plating method and a plating apparatus which can securely form a metal film (protective film) by electroless plating on the exposed surfaces of a base metal, such as interconnects without the formation of voids in the base metal. The...	08/19/2008
7402519	Interconnects having sealing structures to enable selective metal capping layers Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which...	07/22/2008
7402883	Back end of the line structures with liner and noble metal layer A back end of the line (BEOL) structure of a semiconductor device is presented. In one embodiment, the structure may include a first liner layer disposed on an intermediate interconnect structure, the intermediate interconnect structure having an opening disposed be...	07/22/2008
7396756	Top layers of metal for high performance IC's A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an ...	07/08/2008
7393782	Process for producing layer structures for signal distribution Structures for signal distribution are produced by applying a metallic seed layer over a semiconductor body. An insulating layer is applied over the metallic seed layer and openings in the insulating layer are produced by photolithographic patterning of the insulati...	07/01/2008
7368376	Top layers of metal for high performance IC's A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an ...	05/06/2008
7341945	Method of fabricating semiconductor device A method of fabricating a semiconductor device prevents agglomeration of a seed metal layer in a recess. A recess is formed in a dielectric layer formed on or over a wafer. A seed metal layer (e.g., Cu or Cu alloy) is then formed on a bottom face and an inner side f...	03/11/2008
7332813	Semiconductor device A semiconductor device with a metallic region can have a resistance to stress migration and increased reliability. A lower layer wiring made from a barrier metal film (102) and a copper containing metallic film (103) can be formed within an insulating ...	02/19/2008
7329952	Method of fabricating a semiconductor device The semiconductor device comprises a copper interconnection 26b buried in an insulating film 16, and a dummy pattern for chemical mechanical polishing buried in the insulating film 16 near the copper interconnection 26b. The...	02/12/2008
7276441	Dielectric barrier layer for increasing electromigration lifetimes in copper interconnect structures Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The...	10/02/2007
7205667	Semiconductor device having copper wiring A first interlayer insulating film made of insulting material is formed over an underlying substrate. A via hole is formed through the first interlayer insulating film. A conductive plug made of copper or alloy mainly consisting of copper is filled in the via hole. ...	04/17/2007
7205663	Method to increase electromigration resistance of copper using self-assembled organic thiolate monolayers Methods and solutions for forming self assembled organic monolayers that are covalently bound to metal interfaces are presented along with a device containing a self assembled organic monolayer. Embodiments of the present invention utilize self assembled thiolate mo...	04/17/2007
7180191	Semiconductor device and method of manufacturing a semiconductor device A semiconductor device 200 comprises a SiCN film 202 formed on a semiconductor substrate (not shown), a first SiOC film 204 formed thereon, a SiCN film 208 formed thereon, a second SiOC film 210 formed thereon, a SiO2 fi...	02/20/2007
7176577	Semiconductor device A semiconductor device is made up of a first insulating layer having a through hole; a first interconnection which comprises a first conductive layer, a first barrier layer, and a first main interconnection, and a second interconnection connected to one of the fist ...	02/13/2007
7122878	Method to fabricate high reliable metal capacitor within copper back-end process A new method is provided for the creation of a high-reliability metal capacitor as part of back-end processing. A first layer of metal interconnect is created, ac contact point is provided in the surface of the first layer of interconnect aligned with which a capaci...	10/17/2006
7115996	Method to selectively cap interconnects with indium or tin bronzes and/or oxides thereof and the interconnect so capped A method to selectively cap interconnects with indium or tin bronzes and copper oxides thereof is provided. The invention also provides the interconnect and copper surfaces so formed. ...	10/03/2006
6838379	PROCESS FOR REDUCING IMPURITY LEVELS, STRESS, AND RESISTIVITY, AND INCREASING GRAIN SIZE OF COPPER FILLER IN TRENCHES AND VIAS OF INTEGRATED CIRCUIT STRUCTURES TO ENHANCE ELECTRICAL PERFORMANCE OF COPPER FILLER A process for forming copper metal interconnects and copper-filled vias in a dielectric layer on an integrated circuit structure wherein the impurity level of the copper-filled metal lines and copper-filled vias is lowered, resulting in an increase in the average gr...	01/04/2005
6696758	Interconnect structures and a method of electroless introduction of interconnect structures An apparatus including a substrate comprising a device having contact point; a dielectric layer overlying the device with an opening to the contact point; and an interconnect structure disposed in the opening including an interconnect material and a diffe...	02/24/2004
6670639	Copper interconnection The present invention relates to a copper interconnection comprising a copper or copper alloy layer, wherein at least 50% of crystal grains of copper or a copper alloy form twins. A copper interconnection of the present invention is, therefore, highly rel...	12/30/2003
6661093	Semiconductor device For preventing ଱-rays induced soft errors in a semiconductor device in which solder bumps are connected with Cu wirings formed on Al wirings, bump lands connected with solder bumps and Cu wirings connected integrally therewith are constituted of a s...	12/09/2003
6649517	Copper metal structure for the reduction of intra-metal capacitance A new method and structure is provided for the creation of interconnect lines. The cross section of the interconnect lines of the invention, taken in a plane that is perpendicular to the longitudinal direction of the interconnect lines, is a triangle as o...	11/18/2003
6642622	Semiconductor device with protective layer A semiconductor device includes a substrate and a first insulating film provided above the semiconductor substrate. A first interconnecting layer is provided on the first insulating film. A second insulating film is provided above the first interconnectin...	11/04/2003
6639318	Integrated circuit device and its manufacturing method The present invention has an object to provide an integrated circuit device having a Cu wiring, using a barrier layer which facilitates planarization. The present invention relates to an integrated circuit device having a Cu wiring layer, a barrier layer ...	10/28/2003
6635583	Silicon carbide deposition for use as a low-dielectric constant anti-reflective coating The present invention generally provides a process for depositing silicon carbide using a silane-based material with certain process parameters that is useful for forming a suitable ARC for IC applications. The same material may also be used as a barrier ...	10/21/2003
6627093	Method of manufacturing a vertical metal connection in an integrated circuit At least one layer of a dielectric material 3 is deposited on a copper track 1 covered with an encapsulation layer 2. A cavity 6 is etched in the layer of dielectric material at the location of the future vertical connection. At least one protective layer...	09/30/2003
6611458	Semiconductor integrated circuit device To reduce cost of defect redundancy and trimming in a semiconductor integrated circuit having multiple layer wirings and copper wirings, address for salvaging defect of a memory cell array in a semiconductor is stored by using a nonvolatile memory element...	08/26/2003
6580171	Semiconductor wiring device A semiconductor device is structured to include a wiring made of Al, a first insulation film made of silicon oxide including an organic content formed in contact with an upper surface of the wiring, and a second insulation film formed in contact with an u...	06/17/2003
6579789	Method for fabricating metal wiring and the metal wiring In the method for fabricating a metal wiring, an insulation film is formed on a semiconductor substrate. The insulation film has a contact hole exposing the semiconductor substrate. A Ti--Si film is formed over the silicon substrate, and a Ti--Si--N film ...	06/17/2003
6577011	Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same The present invention includes a multilevel air-gap-containing interconnect wiring structure including: a collection of interspersed line levels and via levels, the via levels and line levels containing conductive via and line features embedded in a diele...	06/10/2003
6555911	Semiconductor device and method of manufacturing interconnections thereof using copper and tungsten in predetermined ratios A semiconductor device having a plurality of interconnection layers includes signal lines formed of copper according to a single damascene process, vias formed of tungsten beneath the signal lines according to a single damascene process, and power and gro...	04/29/2003
6552432	Mask on a polymer having an opening width less than that of the opening in the polymer A typical integrated circuit interconnects millions of microscopic transistors and resistors with aluminum wires buried in silicon-dioxide insulation. Yet, aluminum wires and silicon-dioxide insulation are a less attractive combination than gold, silver, ...	04/22/2003
6525428	Graded low-k middle-etch stop layer for dual-inlaid patterning Improved etch selectivity, barrier metal wetting and reduced interconnect capacitance are achieved by implementing damascene processing employing a graded middle etch stop layer comprising a first silicon carbide layer, a silicon-rich layer on the first s...	02/25/2003
6515366	Reduction of metal corrosion in semiconductor devices Reducing metal corrosion, such as copper corrosion, in semiconductor devices, is disclosed. A semiconductor device includes an insulating layer, a metal line, one or more corrosive metal components, and one or more sacrificial corrosive metal components. ...	02/04/2003
6515365	Semiconductor device having a ground plane and manufacturing method thereof A semiconductor device includes at least first and second lower layer wirings provided on a surface of an insulator on a semiconductor substrate, a first interlayer film provided on the insulator to cover surfaces of the first and second lower layer wirin...	02/04/2003
6508919	Optimized liners for dual damascene metal wiring A method of forming diffusion barrier stacks on a dielectric for a dual damascene metal chip-level interconnect, and a diffusion barrier stack produced thereby. Alternating layers of a metal and an electrically resistive diffusion barrier are deposited on...	01/21/2003
6492692	Semiconductor integrated circuit and manufacturing method therefore To decrease the area of a chip, improve the manufacturing efficiency and decrease the cost in a semiconductor device such as a driver integrated circuit having a number of output pads, and an electronic circuit device such as electronic clock. There are d...	12/10/2002
6486533	Metallization structures for microelectronic applications and process for forming the structures A metallized structure for use in a microelectronic circuit is set forth. The metallized structure comprises a dielectric layer, an ultra-thin film bonding layer disposed exterior to the dielectric layer, and a low-Me concentration, copper-Me alloy layer ...	11/26/2002

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Class 257/E23.161 - Principal metal being copper (EPO)