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| Number | Title | Issue Date |
| 7411255 | Dopant barrier for doped glass in memory devices A semiconductor device has a diffusion barrier formed between a doped glass layer and surface structures formed on a substrate. The diffusion barrier includes alumina and optionally a nitride, and has a layer thickness satisfying the high aspect ratio of the gaps be... | 08/12/2008 |
| 7405447 | Silicon rich barrier layers for integrated circuit devices Semiconductor devices and memory cells are formed using silicon rich barrier layers to prevent diffusion of dopants from differently doped polysilicon films to overlying conductive layers or to substrates. A polycilicide gate electrode structure may be formed using ... | 07/29/2008 |
| 7361991 | Closed air gap interconnect structure A closed air gap interconnect structure is described. The structure includes discrete regions of a permanent support dielectric under the interconnect lines so that the lines are substantially surrounded by air except for the discrete regions of the support dielectr... | 04/22/2008 |
| 7282802 | Modified via bottom structure for reliability enhancement The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures de... | 10/16/2007 |
| 7268413 | Bipolar transistors with low-resistance emitter contacts Many integrated circuits include a type of transistor known as a bipolar junction transistor, which has an emitter contact formed of polysilicon. Unfortunately, polysilicon has a relatively high electrical resistance that poses an obstacle to improving switching spe... | 09/11/2007 |
| 7230338 | Semiconductor device that improves electrical connection reliability A semiconductor device including: a semiconductor section in which an element is formed; an insulating layer formed on the semiconductor section; an electrode pad formed on the insulating layer; a contact section formed of a conductive material provided in a contact... | 06/12/2007 |
| 7211479 | Silicon rich barrier layers for integrated circuit devices Semiconductor devices and memory cells are formed using silicon rich barrier layers to prevent diffusion of dopants from differently doped polysilicon films to overlying conductive layers or to substrates. A polycilicide gate electrode structure may be formed using ... | 05/01/2007 |
| 7193326 | Mold type semiconductor device A mold type semiconductor device includes a semiconductor chip including a semiconductor part; a metallic layer; a solder layer; and a metallic member connecting to the semiconductor chip through the metallic layer and the solder layer. The solder layer is made of s... | 03/20/2007 |
| 7187080 | Semiconductor device with a conductive layer including a copper layer with a dopant A method of manufacturing a semiconductor device includes the steps of providing a semiconductor substrate (202), forming a dielectric layer (204) over the semiconductor substrate (202), and etching a trench or a via (206) in the dielectr... | 03/06/2007 |
| 7183649 | Methods and procedures for engineering of composite conductive films by atomic layer deposition A composite film comprised of three layers is formed by ALD on a substrate with a substrate interface surface. A first layer is coupled to the substrate interface surface. The first layer provides adhesion to the substrate interface surface and initiation of layer b... | 02/27/2007 |
| 7157795 | Composite tantalum nitride/tantalum copper capping layer Electromigration and stress migration of Cu interconnects are significantly reduced by forming a composite capping layer comprising a layer of tantalum nitride on the upper surface of the inlaid Cu and a layer of α-Ta on the titanium nitride layer. Embodiments incl... | 01/02/2007 |
| 7148560 | IC chip package structure and underfill process A novel integrated circuit (IC) chip package structure and underfill process which reduces stress applied to corners of a flip chip in an IC package structure during the application of an adhesive material between the flip chip and a carrier substrate is disclosed. ... | 12/12/2006 |
| 7141880 | Metal line stacking structure in semiconductor device and formation method thereof The method for forming a metal line stacking structure according to a preferred embodiment of the present invention comprises: sequentially forming a first barrier metal and a first metal layer on a lower dielectric layer that is disposed over a semiconductor substr... | 11/28/2006 |
| 7119441 | Semiconductor interconnect structure In a semiconductor device, an interlevel insulating film formed between a Cu interconnection, formed by damascene, and an upper metal interconnection layer on it has a multilayered structure made up of a Cu diffusion preventive insulating layer and another insulatin... | 10/10/2006 |
| 7109062 | Semiconductor integrated device including support substrate fastened using resin, and manufacturing method thereof A semiconductor integrated device, provided with a semiconductor chip on which a semiconductor integrated circuit is formed and a support substrate laminated on at least one surface of the semiconductor chip, wherein the semiconductor chip and the support substrate ... | 09/19/2006 |
| 7102232 | Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is ... | 09/05/2006 |
| 7061113 | Semiconductor apparatus, led head, and image forming apparatus A semiconductor apparatus has a substrate to which is attached a thin semiconductor film including at least one semiconductor device. A first interconnecting line formed on the thin semiconductor film makes electrical contact with the semiconductor device. A second ... | 06/13/2006 |
| 6703666 | Thin film resistor device and a method of manufacture therefor The present invention provides a thin film resistor and method of manufacture therefor. The thin film resistor comprises a resistive layer located on a first dielectric layer, first and second contact pads located on the resistive layer, and a second diel... | 03/09/2004 |
| 6693001 | Process for producing semiconductor integrated circuit device A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETs by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity C... | 02/17/2004 |
| 6690077 | Antireflective coating and field emission display device, semiconductor device and wiring line comprising same Titanium aluminum nitrogen ("Ti--Al--N") is deposited onto a semiconductor substrate area to serve as an antireflective coating. For wiring line fabrication processes, the Ti--Al--N layer serves as a cap layer which prevents unwanted reflection of photoli... | 02/10/2004 |
| 6690092 | Multilayer interconnection structure of a semiconductor device In order to solve the aforementioned problems, the present invention provides a semiconductor device having a multilayer interconnection structure, wherein an upper interconnection comprises a first metal layer composed of an aluminum alloy, which is form... | 02/10/2004 |
| 6680538 | Semiconductor device for suppressing detachment of conductive layer A semiconductor device and a method for manufacturing the semiconductor device are provided in which a lower plug electrically connected with an active region of a wafer has a recession, and a conductive layer has a projection fitted into the recession of... | 01/20/2004 |
| 6674170 | Barrier metal oxide interconnect cap in integrated circuits An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer ha... | 01/06/2004 |
| 6664192 | Method for bottomless deposition of barrier layers in integrated circuit metallization schemes Methods are disclosed for selective deposition on desired materials. In particular, barrier materials are selectively formed on insulating surfaces, as compared to conductive surfaces. In the context of contact formation and trench fill, particularly dama... | 12/16/2003 |
| 6653229 | Integrated circuit with a recessed conductive layer An improved method for making an integrated circuit. That method includes forming a first dielectric layer on a substrate, etching a trench into that layer, then filling the trench with a conductive material. The conductive material is then electropolishe... | 11/25/2003 |
| 6650017 | Electrical wiring of semiconductor device enabling increase in electromigration (EM) lifetime A method for manufacturing a semiconductor device having on a silicon substrate semiconductor elements and aluminum (Al) alloy wiring leads as electrically connected thereto is disclosed. The method includes the steps of forming on the silicon substrate a... | 11/18/2003 |
| 6649522 | Etch stop in damascene interconnect structure and method of making An interconnect structure with a plurality of low dielectric constant insulating layers acting as etch stops is disclosed. The low dielectric constant materials act as insulating layers through which trenches and vias are subsequently formed by employing ... | 11/18/2003 |
| 6649511 | Method of manufacturing a seed layer with annealed region for integrated circuit interconnects A manufacturing method provides a semiconductor substrate with a semiconductor device. A dielectric layer is formed on the semiconductor substrate and an opening provided therein. An barrier layer lines the opening and a seed layer is deposited to line th... | 11/18/2003 |
| 6646346 | Integrated circuit metallization using a titanium/aluminum alloy An integrated circuit metallization structure using a titanium/aluminum alloy, and a method to generate such a structure, provide reduced leakage current by allowing mobile impurities such as water, oxygen, and hydrogen to passivate structural defects in ... | 11/11/2003 |
| 6645849 | Method for manufacturing semiconductor device for suppressing detachment of conductive layer A semiconductor device and a method for manufacturing the semiconductor device are provided in which a lower plug electrically connected with an active region of a wafer has a recession, and a conductive layer has a projection fitted into the recession of... | 11/11/2003 |
| 6642145 | Method of manufacturing an integrated circuit with a dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer formed over the semiconductor substrate has an opening provided therein. The dielectric layer is of non-ba... | 11/04/2003 |
| 6639319 | Conductive structure in an integrated circuit A method of forming a local interconnect structure is provided. A first barrier layer comprising sputtered titanium nitride is formed over a topographical structure situated upon a field oxide region within a semiconductor substrate. A hard mask layer com... | 10/28/2003 |
| 6635964 | Metallization structure on a fluorine-containing dielectric and a method for fabrication thereof The present invention is related to a metallization structure on a fluorine-containing dielectric. This metallization structure includes a conductive pattern; a fluorine-containing dielectric; and a barrier layer containing a material, i.e. a near noble m... | 10/21/2003 |
| 6617242 | Method for fabricating interlevel contacts of aluminum/refractory metal alloys A method for fabricating interlevel contacts in semiconductor integrated circuits provides for formation of a contact opening through an insulating layer. A layer of refractory metal, or refractory metal alloy, is deposited over the surface of the integra... | 09/09/2003 |
| 6617689 | Metal line and method of suppressing void formation therein An interconnect line that is enclosed within electrically conductive material is disclosed. The interconnect line, which is useful for electrically connecting devices in an integrated circuit, is defined by an aluminum layer having a bottom surface covere... | 09/09/2003 |
| 6611061 | Tantalum-aluminum-nitrogen material for semiconductor devices Ta--Al--N is formed on a semiconductor device structure, such as a wiring line, to prevent interdiffusion between surrounding layers. Ta--Al--N serves as a diffusion between two conductor layers, a semiconductor layer and a conductor layer, an insulator l... | 08/26/2003 |
| 6608353 | Thin film transistor having pixel electrode connected to a laminate structure An electronic circuit formed on an insulating substrate and having thin-film transistors (TFTs) comprising semiconductor layers. The thickness of the semiconductor layer is less than 1500 Å, e.g., between 100 and 750 Å. A first layer consisting mainly o... | 08/19/2003 |
| 6600174 | Light receiving element and semiconductor laser device A corrosion-resistant conductive layer (TiW layer) formed of a corrosion-resistant material is formed to extend from a bonding pad portion to an interconnection portion of a light receiving element. A semiconductor laser device according to the present in... | 07/29/2003 |
| 6597042 | Contact with germanium layer A contact to a semiconductor substrate including a contact opening extending through an insulating layer to a doped active region of the semiconductor substrate. The contact opening can have a relatively high aspect ratio of 2:1 or greater. The contact fu... | 07/22/2003 |
| 6583051 | Method of manufacturing an amorphized barrier layer for integrated circuit interconnects A manufacturing method for an integrated circuit is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. An amorphized barrier layer lines the open... | 06/24/2003 |
