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| Number | Title | Issue Date |
| 7435679 | Alloyed underlayer for microelectronic interconnects Apparatus and methods of fabricating a microelectronic interconnect having an underlayer which acts as both a barrier layer and a seed layer. The underlayer is formed by co-depositing a noble metal and a barrier material, such as a refractory metal, or formed during... | 10/14/2008 |
| 7425765 | Zinc-aluminum solder alloy A high melting point solder alloy superior in oxidation resistance, in particular a solder alloy provided with both a high oxidation resistance and high melting point suitable for filling fine through holes of tens of microns in diameter and high aspect ratios and f... | 09/16/2008 |
| 7411300 | Agglomeration control using early transition metal alloys Structures and methods of fabricating portions of integrated circuit devices to reduce agglomeration tendencies of high surface-energy metals used in interconnects and contacts. Early transition metals having relatively low surface energies are chosen to form stable... | 08/12/2008 |
| 7400042 | Substrate with adhesive bonding metallization with diffusion barrier A metallization layer that includes a tantalum layer located on the component, a tantalum silicide layer located on the tantalum layer, and a platinum silicide layer located on the tantalum silicide layer. In another embodiment the invention is a component having a ... | 07/15/2008 |
| 7358574 | Semiconductor device having silicide-blocking layer and fabrication method thereof A semiconductor device having a silicide-blocking layer is provided. The device includes a field oxide layer defining an active region, source/drain regions in the active region of a substrate, a gate oxide layer and a gate electrode on the substrate between the sou... | 04/15/2008 |
| 7326652 | Atomic layer deposition using photo-enhanced bond reconfiguration An atomic layer deposition process that reduces defective bonds formed when depositing atomic layers on a substrate or atomic layer when forming an integrated circuit device. As the layers are formed, a substrate or previous layer is exposed to a first reactant. Aft... | 02/05/2008 |
| 7132352 | Method of eliminating source/drain junction spiking, and device produced thereby A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A metallic layer is formed on the semiconductor substrate, and the metallic... | 11/07/2006 |
| 6699781 | Conductive material for integrated circuit fabrication A conductive composition of titanium boronitride (TiBx Ny) is disclosed for use as a conductive material. The titanium boronitride is used as conductive material in the testing and fabrication of integrated circuits. For example, the... | 03/02/2004 |
| 6646456 | Conductive material for integrated circuit fabrication A conductive composition of titanium boronitride (TiBx Ny) is disclosed for use as a conductive material. The titanium boronitride is used as conductive material in the testing and fabrication of integrated circuits. For example, the... | 11/11/2003 |
| 6630688 | Contact structures of wirings and methods for manufacturing the same, and thin film transistor array panels including the same and methods for manufacturing the same First, a conductive material of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed by depositing nitride silicon in the range of more than 300°... | 10/07/2003 |
| 6624514 | Semiconductor device and manufacturing method thereof A semiconductor device includes a middle inter-level insulating film disposed on or above a semiconductor substrate, a conductive layer disposed on the middle inter-level insulating film, and an upper inter-level insulating film disposed on the middle int... | 09/23/2003 |
| 6593653 | Low leakage current silicon carbonitride prepared using methane, ammonia and silane for copper diffusion barrier, etchstop and passivation applications A silicon carbon nitride (SiCN) layer is provided which has a low leakage current and is effective in preventing the migration or diffusion of metal or copper atoms through the SiCN layer. The SiCN layer can be used as a diffusion barrier between a metal ... | 07/15/2003 |
| 6583051 | Method of manufacturing an amorphized barrier layer for integrated circuit interconnects A manufacturing method for an integrated circuit is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. An amorphized barrier layer lines the open... | 06/24/2003 |
| 6541842 | Metal barrier behavior by SiC:H deposition on porous materials A sealing dielectric layer is applied between a porous dielectric layer and a metal diffusion barrier layer. The sealing dielectric layer closes the pores on the surface and sidewalls of the porous dielectric layer. This invention allows the use of a thin... | 04/01/2003 |
| 6518177 | Method of manufacturing a semiconductor device A semiconductor device is formed by a compound film γx made of at least one element selected from metal elements and at least one element γ selected from the group consisting of boron, carbon, and nitrogen on a base layer conta... | 02/11/2003 |
| 6518181 | Conductive material for integrated circuit fabrication A conductive composition of titanium boronitride (TiBx Ny) is disclosed for use as a conductive material. The titanium boronitride is used as conductive material in the testing and fabrication of integrated circuits. For example, the... | 02/11/2003 |
| 6462416 | Gradated barrier layer in integrated circuit interconnects An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer with an opening formed therein is formed on the semiconductor substrate. A barrier layer of barrier... | 10/08/2002 |
| 6462417 | Coherent alloy diffusion barrier for integrated circuit interconnects An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer... | 10/08/2002 |
| 6452273 | Semiconductor integrated circuit device and method of manufacturing the same A semiconductor integrated circuit device and method of manufacturing the same is presented. The device comprises a first conductive line formed on a semiconductor substrate. An insulating layer formed on the first conductive line and the semiconductor su... | 09/17/2002 |
| 6444568 | Method of forming a copper diffusion barrier A silicon carbon nitride (SiCN) layer is provided which has a low leakage current and is effective in preventing the migration or diffusion of metal or copper atoms through the SiCN layer. The SiCN layer can be used as a diffusion barrier between a metal ... | 09/03/2002 |
| 6417087 | Process for forming a dual damascene bond pad structure over active circuitry A process for forming a dual damascene bond pad within an integrated circuit produces a bond pad which is resistant to stress effects and which therefore allows for the bond pad to be formed over active circuitry. The process includes forming a dual damas... | 07/09/2002 |
| 6348732 | Amorphized barrier layer for integrated circuit interconnects An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. An amorphized barrier layer lines t... | 02/19/2002 |
| 6329670 | Conductive material for integrated circuit fabrication A conductive composition of titanium boronitride (TiBx Ny) is disclosed for use as a conductive material. The titanium boronitride is used as conductive material in the testing and fabrication of integrated circuits. For example, the... | 12/11/2001 |
| 6316790 | Active matrix assembly with light blocking layer over channel region Improved thin film transistors resistant to photo-induced current and having improved electrical contact between electrodes and the source or drain regions are provided. The thin film transistors formed in accordance with the invention are particularly we... | 11/13/2001 |
| 6229211 | Semiconductor device and method of manufacturing the same A semiconductor device comprises a base layer, a barrier metal layer formed on the base layer and a metal interconnect formed on the barrier metal layer, the barrier metal layer being made of at least one element selected from metal elements and a... | 05/08/2001 |
| 6215189 | Semiconductor device having interconnect layer and method of manufacturing therefor A highly reliable semiconductor device having a contact hole with a sufficient area can be obtained. An interlevel insulating film is formed on a conductive region having a first width. A through hole which exposes the conductive region is formed at the i... | 04/10/2001 |
| 6037608 | Liquid crystal display device with crossover insulation Improved thin film transistors resistant to photo-induced current and having improved electrical contact between electrodes and the source or drain regions are provided. The thin film transistors formed in accordance with the invention are particularly we... | 03/14/2000 |
| 5897370 | High aspect ratio low resistivity lines/vias by surface diffusion A method of filling high aspect ratio vias and lines on the upper surface of a substrate prevents voids from being formed therein. The method comprises the steps of filling the lines and vias by surface diffusion at room temperature and at a pressure of 1... | 04/27/1999 |
| 5877084 | Method for fabricating high aspect ratio low resistivity lines/vias by surface reaction A structure and method for fabricating circuits which use field effect transistors (FETs), bipolar transistors, or BiCMOS (combined Bipolar/Complementary Metal Oxide Silicon structures), uses low temperature germanium gas flow to affect metals and alloys ... | 03/02/1999 |
| 5856026 | High aspect ratio low resistivity lines/vias by surface diffusion A structure and method for fabricating circuits which use field effect transistors (FETs), bipolar transistors, or BiCMOS (combined Bipolar/Complementary Metal Oxide Silicon structures), uses low temperature germanium gas flow to affect metals and alloys ... | 01/05/1999 |
| 5731245 | High aspect ratio low resistivity lines/vias with a tungsten-germanium alloy hard cap A structure and method for fabricating circuits which use field effect transistors (FETs), bipolar transistors, or BiCMOS (combined Bipolar/Complementary Metal Oxide Silicon structures), uses low temperature germanium gas flow to affect metals and alloys ... | 03/24/1998 |
| 5712510 | Reduced electromigration interconnection line The electromigration lifetime of a metal interconnection line is increased by adjusting the length of the interconnection line, or providing longitudinally spaced apart holes or vias, to optimize the Backflow Potential Capacity of the metal interconnectio... | 01/27/1998 |
| 5689139 | Enhanced electromigration lifetime of metal interconnection lines The electromigration lifetime of a metal interconnection line is increased by adjusting the length of the interconnection line or providing longitudinally spaced apart holes or vias to optimize the backflow potential capacity of the metal interconnection ... | 11/18/1997 |
| 5656547 | Method for making a leadless surface mounted device with wrap-around flange interface contacts A flange interface for wrap-around contact regions formed in fabricating semiconductor devices provides for a durable and reliable electrical bond. A first layer having a first material is formed over the first side of a wafer. A trench is formed from the... | 08/12/1997 |
| 5650664 | Connector effecting an improved electrical connection and a semiconductor apparatus using such connector A semiconductor apparatus exhibiting excellent contact characteristics, high operational speed and low electric power consumption is realized by forming a layer made of Ti or a Ti compound between an oxide containing indium such as a thin ITO film and a S... | 07/22/1997 |
| 5650637 | Active matrix assembly Improved thin film transistors resistant to photo-induced current and having improved electrical contact between electrodes and the source or drain regions are provided. The thin film transistors formed in accordance with the invention are particularly we... | 07/22/1997 |
| 5573959 | Method of forming a liquid crystal device Improved thin film transistors resistant to photo-induced current and having improved electrical contact between electrodes and the source or drain regions are provided. The thin film transistors formed in accordance with the invention are particularly we... | 11/12/1996 |
| 5557149 | Semiconductor fabrication with contact processing for wrap-around flange interface A flange interface for wrap-around contact regions formed in fabricating semiconductor devices provides for a durable and reliable electrical bond. A first layer having a first material is formed over the first side of a wafer. A trench is formed from the... | 09/17/1996 |
| 5552615 | Active matrix assembly with double layer metallization over drain contact region Improved thin film transistors resistant to photo-induced current and having improved electrical contact between electrodes and the source or drain regions are provided. The thin film transistors formed in accordance with the invention are particularly we... | 09/03/1996 |
| 5510651 | Semiconductor device having a reducing/oxidizing conductive material The present invention includes a semiconductor device having a layer including an elemental metal and its conductive metal oxide, wherein the layer is capable being oxidized or reduced preferentially to an adjacent region of the device. The present invent... | 04/23/1996 |
