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| Number | Title | Issue Date |
| 7429797 | Electronic device and carrier substrate Consistent with an example embodiment, an electronic device comprises a semiconductor device, particularly an integrated circuit, and a carrier substrate with conductive layers on the first side and the second side, and voltage supply and ground connections mutually... | 09/30/2008 |
| 7414275 | Multi-level interconnections for an integrated circuit chip Multilevel metallization layouts for an integrated circuit chip including transistors having first, second and third elements to which metallization layouts connect. The layouts minimize current limiting mechanism including electromigration by positioning the connec... | 08/19/2008 |
| 7375423 | Semiconductor device A semiconductor device includes a pad composed of plural wiring layers and a power supply ring to provide a power supply provided through the pad for the power supply to an internal circuit, and the pad for the power supply and the power supply ring are connected by... | 05/20/2008 |
| 7365415 | High frequency semiconductor device A semiconductor device has a mounting substrate and a semiconductor package mounted on the mounting substrate. The mounting substrate has a substrate body, input/output line conductors on the upper surface of the substrate body, a front-face grounding conductor on t... | 04/29/2008 |
| 7348214 | Integrated circuit package with improved power signal connection An integrated circuit (IC) package includes a substrate and an IC die mounted on a first side of the substrate. The IC package also includes a plurality of capacitors mounted on a second side of the substrate. The second side is opposite to the first side. The IC pa... | 03/25/2008 |
| 7314788 | Standard cell back bias architecture An apparatus including, in one embodiment, a CMOS device cell including at least first and second CMOS transistors having first and second CMOS transistor doped regions in first and second doped wells, respectively, wherein each of the first and second CMOS transist... | 01/01/2008 |
| 7312511 | Semiconductor device with electrically isolated ground structures This invention provides a high frequency power module which is incorporated into a mobile phone and which incorporates high frequency portion analogue signal processing ICs including low noise amplifiers which amplify an extremely weak signal therein. A semiconducto... | 12/25/2007 |
| 7279798 | High wireability microvia substrate The escape of signals from a semiconductor chip to a printed wiring board in a flip chip/ball grid array assembly is improved by repositioning the signals from the chip through the upper signal layers of the carrier. This involves fanning out the circuit lines throu... | 10/09/2007 |
| 7253513 | High-frequency switch device and electronic device using the same A switch device includes a semiconductor chip, and at least two switches formed on the semiconductor chip. Ground parts of the at least two switches are arranged between said at least two switches. ... | 08/07/2007 |
| 7253516 | Electronic device and carrier substrate for same Consistent with an example embodiment, an electronic device comprises an integrated circuit and a carrier substrate with a bottom and top conductive layer, and is provided with voltage supply, ground and signal transmission connections. In order to enable the use of... | 08/07/2007 |
| 7232705 | Integrated circuit bond pad structures and methods of making A bond pad structure for an integrated circuit includes first and second active devices formed in a substrate, first and second buses above the first and second active devices, respectively, a bond pad above the first and second buses, first interconnections between... | 06/19/2007 |
| 7227200 | Metal I/O ring structure providing on-chip decoupling capacitance There are provided a metal I/O ring structure for a semiconductor chip and a decoupling capacitance structure using the same. In the Metal I/O ring structure, a plurality of first metal lines are formed on a first metal layer and connected with a power supply voltag... | 06/05/2007 |
| 7227202 | Semiconductor device and cell A cell 100 includes three wiring layers (a gate electrode layer, a source/drain electrode layer and a terminal layer) on a semiconductor substrate including transistors formed thereon. One of the wiring layers (the terminal layer) in which input terminals ... | 06/05/2007 |
| 7187071 | Composite electronic component A composite electronic component having a multi-layer wiring board, a first power terminal electrode, a second power terminal electrode, an external connection power supply terminal, a surface-mounted component, an insulator, and a power supply pattern. The first an... | 03/06/2007 |
| 7170114 | Semiconductor device A chip size is remarkably reduced by providing effective layout of the I/O buffers. Since a large capacity non-volatile memory is arranged, bonding pads are arranged at the area near each side of the rectangular shape semiconductor chip and the I/O buffers are arran... | 01/30/2007 |
| 7148535 | Zero capacitance bondpad utilizing active negative capacitance The present invention is an apparatus and system for reducing bondpad capacitance of an integrated circuit. Circuitry of the present invention may produce a negative capacitance approximately equal in magnitude to the capacitance associated with the bondpad and ther... | 12/12/2006 |
| 7125752 | Methods for making microwave circuits including a ground plane In a method for making a microwave circuit, a first dielectric is deposited over a ground plane, and then a conductor is formed on the first dielectric. A second dielectric is then deposited over the conductor and first dielectric, thereby encapsulating the conducto... | 10/24/2006 |
| 7109578 | Semiconductor device and electronic equipment using the same Crosstalk is suppressed low even when one surface of a multi-layer board seats a semiconductor integrated circuit of the BGA type and peripheral circuit components. Of a plurality of BGA bumps arranged on the back surface of a semiconductor integrated circuit chip, ... | 09/19/2006 |
| 6925026 | Semiconductor device adapted for power shutdown and power resumption A semiconductor device that achieves high speed and low power consumption that can be used in a real-time system by preventing held data from disappearing at the time of power shutdown and sharply rising power while also preventing a through-current at the time of p... | 08/02/2005 |
| 6683476 | Contact ring architecture An integrated circuit with a VDDio bus line disposed on a first layer of the integrated circuit. The VDDio bus line is disposed along a length, and has a first width transverse to the length. A VSSio bus line is dispose on a second layer of the integrated... | 01/27/2004 |
| 6683336 | SEMICONDUCTOR INTEGRATED CIRCUIT, SUPPLY METHOD FOR SUPPLYING MULTIPLE SUPPLY VOLTAGES IN SEMICONDUCTOR INTEGRATED CIRCUIT, AND RECORD MEDIUM FOR STORING PROGRAM OF SUPPLY METHOD FOR SUPPLYING MULTIPLE SUPPLY VOLTAGES IN SEMICONDUCTOR INTEGRATED CIRCUIT A semiconductor integrated circuit, a supply method of supplying multiple supply voltages therefor, and a record medium for storing a program of the supply method for supplying multiple voltages therefor in which a first cell to which multiple supply volt... | 01/27/2004 |
| 6680512 | Semiconductor device having an integral protection circuit A CMOS device with an integral reverse connection protection circuit having a low impedance region, whose impedance becomes lowest when a Vcc pad to which is to be supplied power supply voltage and a GND pad to which is to be supplied ground potential are... | 01/20/2004 |
| 6677781 | Semiconductor integrated circuit device A common power source line has first power supply points and second power supply points. The first power supply points are provided for supplying electric power to buffer circuits of low-frequency signal pads, while the second power supply points are prov... | 01/13/2004 |
| 6675367 | Semiconductor integrated circuits and method for designing the same A method of designing a semiconductor integrated circuit makes it possible to reduce the amount of manual routing of a power wire. After a VDD power wire for a circuit block and a VSS power wire for the circuit block have been routed... | 01/06/2004 |
| 6661100 | Low impedance power distribution structure for a semiconductor chip package A low impedance power distribution structure and method for substrate packaging of semiconductor chips containing very large scale integrated circuit (VLSI) circuits, such as microprocessors and associated memory, is presented. The power distribution stru... | 12/09/2003 |
| 6657291 | Combined resistor-capacitor elements for decoupling in electronic packages The present invention is a method and apparatus for electrically decoupling conductors used to distribute power and ground potentials in electronic packages and chips. Specifically, the present invention utilizes Absorbing Plane Terminators (APTs), which ... | 12/02/2003 |
| 6657310 | Top layers of metal for high performance IC's A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or pol... | 12/02/2003 |
| 6657275 | Pad and via placement design for land side capacitors An integrated circuit package and land side capacitor with reduced power delivery loop inductance. The capacitor pads have vias that lie underneath the land side capacitor, and have interposed digits.... | 12/02/2003 |
| 6657285 | Semiconductor anti-interference band for integrated circuit A semiconductor anti-interference band distributed on peripheries of partial of regional circuits in an integrated circuit is assembled by an unequal number of PNP structures; two metal bands are disposed on the surface layer of the integrated circuit, wh... | 12/02/2003 |
| 6657307 | Semiconductor integrated circuit having functional macro with improved power line connection structure In a semiconductor integrated circuit having a functional macro, plural first and second power lines extending over the functional macro and supplying first-level and second-level voltages respectively to the functional macro are electrically connected th... | 12/02/2003 |
| 6657910 | Semiconductor device having internal power terminals including a positive power terminal and a negative power terminal A semiconductor device having internal power terminals including a positive power terminal supplying a high potential and a negative power terminal supplying a low potential to the internal device region of a semiconductor chip in which the positive power... | 12/02/2003 |
| 6653563 | Alternate bump metallurgy bars for power and ground routing An apparatus, including a die having a surface, further including an array of electrically conductive bumps; and a plurality of electrically conductive bars positioned within the array of electrically conductive bumps.... | 11/25/2003 |
| 6653726 | Power redistribution bus for a wire bonded integrated circuit The subject matter described herein involves a wire bonded integrated circuit (IC) that includes a power distribution grid, or power redistribution bus, within a single layer, e.g. the topmost metallization layer, of the IC chip. Electrical conductors in ... | 11/25/2003 |
| 6653857 | Increasing implicit decoupling capacitance using asymmetric shieldings An integrated circuit that asymmetrically shields a signal to increase decoupling capacitance is provided. The signal is asymmetrically shielded based on a probability of the signal being at a specific value. Further, a computer system that uses asymmetri... | 11/25/2003 |
| 6649509 | Post passivation metal scheme for high-performance integrated circuit devices A new post-passivation metal interconnect scheme is provided over the surface of a IC device that has been covered with a conventional layer of passivation. The metal scheme of the invention comprises, overlying a conventional layer of passivation, thick ... | 11/18/2003 |
| 6645842 | Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method There are disclosed a semiconductor integrated circuit device, a semiconductor integrated circuit wiring method and a cell arranging method, which can reduce delay in a semiconductor integrated circuit and improve noise resistibility, achieve facility of ... | 11/11/2003 |
| 6638793 | Methodology to pack standard staggered bond input-output buffer into linear input-output buffer A new method is provided that allows placing or stacking staggered bond I/O buffers into linear bond I/O buffers. The bond pads are linearly arranged, the interface between the staggered bond pad I/O buffers and the linearly arranged bond pads is achieved... | 10/28/2003 |
| 6635515 | Method of manufacturing a semiconductor device having signal line above main ground or main VDD line A semiconductor device is disclosed, by which the parasitic capacitance of each signal line can be decreased, the time necessary for developing the device can be decreased, and which has a structure for simply and quickly performing the characteristic eva... | 10/21/2003 |
| 6628138 | Increasing decoupling capacitance using preferential shields An integrated circuit that preferentially shields a signal to increase decoupling capacitance is provided. The signal is preferentially shielded based on a probability of the signal being at a specific value. Further, a method for increasing an amount of ... | 09/30/2003 |
| 6624515 | Microelectronic die including low RC under-layer interconnects A microelectronic die comprises a first area, a second area and an under-layer of conductive material formed in the second area to interconnect components. A method of making a microelectronic die comprises forming a layer of insulative material on a subs... | 09/23/2003 |
