Quotables
"During my service in the United States Congress, I took the initiative in creating the Internet."
Al Gore ; The basis for the later misquote by US Republicans that Gore had "invented" the Internet. Gore was the leading political champion of the modern-day Internet.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7432198 | Semiconductor devices and methods of forming interconnection lines therein An example disclosed semiconductor device includes a semiconductor substrate, a lower interlayer insulating layer formed on the substrate, a lower wire formed on the lower interlayer insulating layer, and an upper interlayer insulating layer which is formed on the l... | 10/07/2008 |
| 7414275 | Multi-level interconnections for an integrated circuit chip Multilevel metallization layouts for an integrated circuit chip including transistors having first, second and third elements to which metallization layouts connect. The layouts minimize current limiting mechanism including electromigration by positioning the connec... | 08/19/2008 |
| 7394154 | Embedded barrier for dielectric encapsulation A semiconductor interconnect structure and method providing an embedded barrier layer to prevent damage to the dielectric material during or after Chemical Mechanical Polishing. The method employs a combination of an embedded film, etchback, using either selective C... | 07/01/2008 |
| 7372153 | Integrated circuit package bond pad having plurality of conductive members An integrated circuit package bond pad includes an insulating layer and an electrode located over the insulating layer. The electrode has a first surface configured to be bonded to external circuitry and a second surface opposite the first surface. A plurality of co... | 05/13/2008 |
| 7291923 | Tapered signal lines In an integrated circuit, a layer including a plurality of conductive wires is described. A first wire, having sidewalls, is tapered from a proximal end which has a first width to a distal end which has a second width, to reduce width from the first width to the sec... | 11/06/2007 |
| 7274109 | Modular bonding pad structure and method A semiconductor die includes a plurality of drivers and a plurality of bonding pads. Each driver is formed by a plurality of interconnected modules and has an associated bonding pad to which at least one of the modules of the driver is electrically connected. The mo... | 09/25/2007 |
| 7265448 | Interconnect structure for power transistors An integrated circuit according to the present invention includes first, second and third plane-like metal layers. A first transistor has a first control terminal and first and second terminals. The second terminal communicates with the first plane-like metal layer.... | 09/04/2007 |
| 7245016 | Circuit layout structure A circuit layout structure for a chip is provided. The chip has a bonding pad area, a nearby device area, and a substrate. The circuit layout structure essentially comprises a plurality of circuit layers, a plurality of dielectric layers and a plurality of vias. The... | 07/17/2007 |
| 7235872 | Bow control in an electronic package A package including a package substrate, a die-substrate assembly including a substrate including a plurality of layers including a layer having a mesh to stiffen the substrate adapted to mount one or more dice, one or more dice mounted on the substrate and a moldin... | 06/26/2007 |
| 7205664 | Semiconductor device and method for manufacturing the same A semiconductor device including a multilevel wiring with a small interwiring capacitance is provided by comprising a wiring, a conductive film formed on an upper surface of the wiring to prevent diffusion of a wiring material, and an insulating film which is consti... | 04/17/2007 |
| 7105877 | Conductive line structure A conductive line Structure. In one embodiment of the invention, a conductive line includes at least two outer conductive portions, an inner conductive portion between the outer conductive portions, separated from the outer conductive portions by at least two trench... | 09/12/2006 |
| 6784472 | Semiconductor device and method for fabricating the same A semiconductor device comprises a first transistor 38a having a first gate electrode 22; a second transistor 38b having a second gate electrode 34 which is different from the first gate electrode; an insulation film 28 | 08/31/2004 |
| 6703710 | Dual damascene metal trace with reduced RF impedance resulting from the skin effect The RF impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fingers that extend away from the base region. When formed to have a number of loops, the metal trace forms an inductor ... | 03/09/2004 |
| 6696359 | Design layout method for metal lines of an integrated circuit A process to enhance metal line layout designs is provided and includes two separate control spaces to address capacitive issues along speed sensitive pathways in an integrated circuit structure without negatively impacting the Werner Fill process. One co... | 02/24/2004 |
| 6689681 | Semiconductor device and a method of manufacturing the same A semiconductor device includes a first insulating layer which is formed above a semiconductor substrate including a plurality of semiconductor elements and which includes lower-layer damascene wiring, a second insulating layer which is formed on the firs... | 02/10/2004 |
| 6690580 | Integrated circuit structure with dielectric islands in metallized regions This disclosure describes use of dielectric islands embedded in metallized regions of a semiconductor device. The islands are formed in a cavity of a dielectric layer, as upright pillars attached at their base to an underlying dielectric. The islands brea... | 02/10/2004 |
| 6677636 | Structure for reducing contact aspect ratios An intermediate metal plug is used to raise the platform to which contact is to be made. In the illustrated process, a partial bit line plug is formed adjacent a stacked capacitor, and an interlevel dielectric formed over the capacitor. The bit line conta... | 01/13/2004 |
| 6674166 | Flip-chip integrated circuit routing to I/O devices Tile-based routing between a bump pad and an input/output (I/O) device for implementation on a flip-chip integrated circuit (IC) die. A trace is routed between the bump pad and a position corresponding to a first I/O slot, the first I/O slot being at leas... | 01/06/2004 |
| 6670238 | Method and structure for reducing contact aspect ratios An intermediate metal plug is used to raise the platform to which contact is to be made. In the illustrated process, a partial bit line plug is formed adjacent a stacked capacitor, and an interlevel dielectric formed over the capacitor. The bit line conta... | 12/30/2003 |
| 6667235 | Semiconductor device and manufacturing method therefor An undercut portion is provided in the side surface of a wiring pattern formed over the electrode terminal forming surface of a semiconductor element so that when the top of the electrode terminal forming surface of the semiconductor element is sealed, a ... | 12/23/2003 |
| 6657305 | Semiconductor recessed mask interconnect technology A metal plus low dielectric constant (low-k) interconnect structure is provided for a semiconductor device wherein adjacent regions in a surface separated by a dielectric have dimensions in width and spacing in the sub 250 nanometer range, and in which re... | 12/02/2003 |
| 6649517 | Copper metal structure for the reduction of intra-metal capacitance A new method and structure is provided for the creation of interconnect lines. The cross section of the interconnect lines of the invention, taken in a plane that is perpendicular to the longitudinal direction of the interconnect lines, is a triangle as o... | 11/18/2003 |
| 6627557 | Semiconductor device and method for manufacturing the same Disclosed is a method of manufacturing a semiconductor device, which comprises the steps of forming an insulating film or a metal film on a surface of a semiconductor substrate, forming at least two kinds of mask on a surface of the insulating film or the... | 09/30/2003 |
| 6624514 | Semiconductor device and manufacturing method thereof A semiconductor device includes a middle inter-level insulating film disposed on or above a semiconductor substrate, a conductive layer disposed on the middle inter-level insulating film, and an upper inter-level insulating film disposed on the middle int... | 09/23/2003 |
| 6597067 | Self-aligned, lateral diffusion barrier in metal lines to eliminate electromigration An interconnection wiring structure in an integrated circuit chip designed to eliminate electromigration. The structure includes segments of aluminum interspersed with segments of refractory metal, wherein each aluminum segment is followed by a segment of... | 07/22/2003 |
| 6593235 | Semiconductor device with a tapered hole formed using multiple layers with different etching rates A semiconductor device having an improved contact hole through an interlayer insulator. A first insulating film comprising silicon nitride is deposited. A second insulating film comprising silicon oxide is deposited on the first insulating film. The depos... | 07/15/2003 |
| 6593654 | Semiconductor device and method for manufacturing same An SiO2 layer and an SiN layer are alternately stacked in regions 1 and 2 where the wiring film must be thin and thick, respectively, in such a manner that the stacked SiO2 and SiN layers constitute first through sixth interlayer ins... | 07/15/2003 |
| 6586815 | Semiconductor device having dummy interconnection and method for manufacturing the same A semiconductor device having an array of dummy interconnections in a fuse window are proposed. The each dummy interconnection comprised of a fuse body scheduled to be blown away by laser beam, a fuse wiring extended up to the bottom of the fuse body from... | 07/01/2003 |
| 6555462 | Semiconductor device having stress reducing laminate and method for manufacturing the same A semiconductor device has a stress reducing laminate. Grooves are formed on the surface of a material layer selected from a multilayer structure of the semiconductor device, for example, a conductive layer. The cross sections of the grooves are semicircu... | 04/29/2003 |
| 6548883 | Reduced RC between adjacent substrate wiring lines A void is defined between adjacent wiring lines to minimize RC coupling. The void has a low dielectric value approaching 1.0. For one approach, hollow silicon spheres define the void. The spheres are fabricated to a known inner diameter, wall thickness an... | 04/15/2003 |
| 6544884 | Semiconductor device and method of fabricating same A semiconductor device capable of operating at a high speed or of having many functions. In this device, delamination of buried electrodes is prevented and thus high reliability is offered. The depth A of contact holes, the minimum linewidth R of a lower ... | 04/08/2003 |
| 6541862 | Semiconductor device including a plurality of interconnection layers, manufacturing method thereof and method of designing semiconductor circuit used in the manufacturing method A semiconductor device including an interconnection structure having superior electrical characteristics and allowing higher speed of operation and lower power consumption even when miniaturized, manufacturing method thereof and a method of designing a se... | 04/01/2003 |
| 6541340 | Method of manufacturing a semiconductor device with a concave trench A semiconductor device and a method of manufacturing the same are provided which are novel and fully improved and are capable of lowering satisfactorily a high-frequency resistance or direct current resistance in a signal line. The semiconductor device is... | 04/01/2003 |
| 6531779 | Multi-layer interconnection structure in semiconductor device and method for fabricating same A semiconductor device having a multi-layer interconnection structure including bottom interconnects and top interconnects including a first top interconnect having a maximum thickness and a second top interconnect having a thickness thinner than that of ... | 03/11/2003 |
| 6524941 | Sub-minimum wiring structure A semiconductor wiring structure positioned between plurality conductors, comprisies spacers positioned on adjacent ones of the conductors and at least one wiring element positioned between the spacers.... | 02/25/2003 |
| 6525426 | Subresolution features for a semiconductor device An integrated circuit having at least one electrical interconnect for connecting at least two components and a process for forming the same are disclosed. The integrated circuit comprises: a substrate, a plurality of adjacent conductive strips, a layer of... | 02/25/2003 |
| 6504189 | Semiconductor device having a microstrip line A microstrip line includes a first conductor pattern formed on a substrate, a second conductor pattern formed on the first conductor pattern with a width substantially identical with a width of the first conductor pattern, and a third conductor pattern fo... | 01/07/2003 |
| 6492734 | Semiconductor device including damascene wiring and a manufacturing method thereof A semiconductor device includes a first insulating layer which is formed above a semiconductor substrate including a plurality of semiconductor elements and which includes lower-layer damascene wiring, a second insulating layer which is formed on the firs... | 12/10/2002 |
| 6489689 | Semiconductor device Two NMOS transistors and two PMOS transistors are provided on a substrate. Power supply lines VDD and VSS connected to the transistors are provided in the second wiring layer. A metal line is provided in the third wiring layer, which is the uppermost wiri... | 12/03/2002 |
| 6489684 | Reduction of electromigration in dual damascene connector As current densities through wiring in integrated circuits increases, so too do failures due to electromigration. Such failure almost always occur in vias located at the ends of long lines. The present invention solves this problem by introducing, as part... | 12/03/2002 |
