Class 257/E23.151 - Geometry or layout of interconnection structure (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E23.142. This subclass
No. of patents: 451
Last issue date: 10/07/2008

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Number	Title	Issue Date
7432597	Semiconductor device and method of manufacturing the same In a semiconductor device including a memory region and a logic region, one or more of a plurality of logic transistor connection plugs, buried in a first insulating layer and connected to a diffusion layer of a logic transistor, are left unconnected to a first inte...	10/07/2008
7414275	Multi-level interconnections for an integrated circuit chip Multilevel metallization layouts for an integrated circuit chip including transistors having first, second and third elements to which metallization layouts connect. The layouts minimize current limiting mechanism including electromigration by positioning the connec...	08/19/2008
7394115	Semiconductor integrated circuit device having clock signal transmission line and wiring method thereof A clock signal transmission line in the semiconductor integrated circuit device includes a plurality of straight portions arranged side by side in a predetermined direction and a plurality of bent portions connecting the respective straight portions. At least two of...	07/01/2008
7348674	Low capacitance wiring layout Integrated circuits having multi-level wiring layouts designed to inhibit the capacitive-resistance effect, and a method for fabricating such integrated circuits, is described. The integrated circuits have at least two planes of wiring adjacent to each other and ext...	03/25/2008
7332818	Multi-chip electronic package with reduced line skew and circuitized substrate for use therein An electronic package which includes a circuitized substrate having at least two electrical components positioned thereon. The package includes patterns of contact sites, each for having one of the components coupled thereto. The patterns of contact sites in turn ar...	02/19/2008
7332753	Semiconductor device, wafer and method of designing and manufacturing the same A process margin of an interconnect is to be expanded, to minimize the impact of vibration generated during a scanning motion of a scanning type exposure equipment. In a semiconductor device, the interconnect handling a greater amount of data (frequently used interc...	02/19/2008
7329952	Method of fabricating a semiconductor device The semiconductor device comprises a copper interconnection 26b buried in an insulating film 16, and a dummy pattern for chemical mechanical polishing buried in the insulating film 16 near the copper interconnection 26b. The...	02/12/2008
7329605	Semiconductor structure formed using a sacrificial structure A method of forming a buried conductive structure in a semiconductor device includes the steps of forming a first insulating layer on a semiconductor layer; forming a sacrificial structure on at least a portion of the first insulating layer; forming a second insulat...	02/12/2008
7328419	Place and route tool that incorporates a metal-fill mechanism Disclosed is a method, system, and article of manufacture for a one-pass approach for implementing metal-fill for an integrated circuit. Also disclosed is a method, system, and article of manufacture for implementing metal-fill that is coupled to a tie-off connectio...	02/05/2008
7307345	Crossbar-array designs and wire addressing methods that tolerate misalignment of electrical components at wire overlap points Various embodiments of the present invention are directed to crossbar array designs that interfaces wires to address wires, despite misalignments between electrical components and wires. In one embodiment, a nanoscale device may be composed of a first layer of two o...	12/11/2007
7245016	Circuit layout structure A circuit layout structure for a chip is provided. The chip has a bonding pad area, a nearby device area, and a substrate. The circuit layout structure essentially comprises a plurality of circuit layers, a plurality of dielectric layers and a plurality of vias. The...	07/17/2007
7235855	Semiconductor device having a layout configuration for minimizing crosstalk Over a memory cell array region of a static RAM (random access memory), dummy wire patterns are formed such that each dummy wire pattern covers 2×2 horizontally and vertically-adjacent intersection points of word lines and bit lines, and horizontally-running wire c...	06/26/2007
7230338	Semiconductor device that improves electrical connection reliability A semiconductor device including: a semiconductor section in which an element is formed; an insulating layer formed on the semiconductor section; an electrode pad formed on the insulating layer; a contact section formed of a conductive material provided in a contact...	06/12/2007
7217962	Wire mesh patterns for semiconductor devices Different patterns of interconnects for connecting wells in a semiconductor device are described. For example, a semiconductor device may include n-wells and p-wells arrayed in rows and columns that lie on a rectilinear grid. Electrically conductive interconnects li...	05/15/2007
7194716	Apparatus and methods for cell models for timing and power analysis A system for analyzing a circuit includes a computer. The computer operates on a model of the circuit. The model has an input, an output, and multiple controlled sources. The computer is configured to supply a stimulus to the input of the model of the circuit. The i...	03/20/2007
7186639	Metal interconnection lines of semiconductor devices and methods of forming the same Metal interconnection lines of semiconductor devices and methods of forming the same are disclosed. Improved reliability is achieved in a disclosed metal line of a semiconductor device by preventing metal layers from eroding and preventing metal lines from being des...	03/06/2007
7180168	Stacked semiconductor chips A groove is formed on a semiconductor substrate having integrated circuits and electrodes from a first surface. An insulating layer is formed on an inner surface of the groove. A conductive layer is formed on the insulating layer above the inner surface of the groov...	02/20/2007
7160799	Define via in dual damascene process The invention includes a process for manufacturing an integrated circuit, comprising providing a substrate comprising a dielectric layer over a conductive material, depositing a hardmask over the dielectric layer, applying a first photoresist over the hardmask and p...	01/09/2007
7141882	Semiconductor wafer device having separated conductive patterns in peripheral area and its manufacture method A method of manufacturing a semiconductor wafer device, including the steps of: (a) forming lower wiring patterns over a semiconductor wafer, the lower wiring patterns being connected to semiconductor elements in a circuit area; (b) forming an interlevel insulating ...	11/28/2006
7138714	Via barrier layers continuous with metal line barrier layers at notched or dielectric mesa portions in metal lines The present invention provides an interconnect structure that includes a diffusion barrier which is positioned within the structure in a fashion that increases the reliability and lifetime of the interconnect structure. ...	11/21/2006
7115497	Method for forming storage node contact plug of DRAM (dynamic random access memory) A method for forming a storage node contact plug of a dynamic random access memory includes forming insulating layers on an overall surface of a semiconductor substrate having a plurality of buried contact plugs, etching the insulating layers down to a top surface o...	10/03/2006
7071099	Forming of local and global wiring for semiconductor product Methods of forming different back-end-of-line (BEOL) wiring for different circuits on the same semiconductor product, i.e., wafer or chip, are disclosed. In one embodiment, the method includes simultaneously generating BEOL wiring over a first circuit using a dual d...	07/04/2006
7007247	Method and mechanism for RTL power optimization The present invention provides a method and mechanism for optimizing the power consumption of a micro-electronic circuit. According to an embodiment, when optimizing the power consumption of a micro-electronic circuit, one or more candidates for applying one or more...	02/28/2006
6971074	Layout device A layout device includes a processing type setting part for classifying a layout of a semiconductor integrated circuit in every area in accordance with the percentage voltage drop in the circuit, and for extracting a processing target portion composed of a group of ...	11/29/2005
6794674	Integrated circuit device and method for forming the same In an integrated circuit device, element power supply lines connected to a circuit containing a plurality of cells, element ground lines connected thereto, a trunk power supply line connected to each of the element power supply lines, and a trunk ground line connect...	09/21/2004
6696359	Design layout method for metal lines of an integrated circuit A process to enhance metal line layout designs is provided and includes two separate control spaces to address capacitive issues along speed sensitive pathways in an integrated circuit structure without negatively impacting the Werner Fill process. One co...	02/24/2004
6690045	Semiconductor device with reduced CMP dishing A semiconductor device comprises a plurality of superposed layers including a predetermined layer provided, in a peripheral part of a chip, with a dummy pattern of a material that is the same as that forming a wiring pattern formed in the same predetermin...	02/10/2004
6683382	Semiconductor device having an interconnect layer with a plurality of layout regions having substantially uniform densities of active interconnects and dummy fills A semiconductor device with an interconnect layer having a plurality of layout regions of active interconnects and dummy fills for uniform planarization. In one embodiment, the device will have at least one interconnect layer with a plurality of layout re...	01/27/2004
6680539	Semiconductor device, semiconductor device pattern designing method, and semiconductor device pattern designing apparatus Patterns to be included in a multi-layer wiring structure of a semiconductor device are designed layer by layer. Functional patterns 92 necessary for implementing functions of the semiconductor device are formed first. A plurality of types of dummy patter...	01/20/2004
6678951	Method of forming electrical interconnects having electromigration-inhibiting plugs A method is provided for forming an electrical conductors, comprising forming electrically conductive segments incorporating electromigration-inhibiting plugs. A row of windows is formed in a planar surface and electromigration-inhibiting material is depo...	01/20/2004
6677236	Semiconductor device fabrication method for interconnects that suppresses loss of interconnect metal A semiconductor device fabrication method includes forming a first interconnect and a second interconnect from aluminum or aluminum alloy. The first and second interconnects are formed at different layers and are connected to each other via metal not incl...	01/13/2004
6674166	Flip-chip integrated circuit routing to I/O devices Tile-based routing between a bump pad and an input/output (I/O) device for implementation on a flip-chip integrated circuit (IC) die. A trace is routed between the bump pad and a position corresponding to a first I/O slot, the first I/O slot being at leas...	01/06/2004
6664641	Wiring structure for an integrated circuit A wire width and a wiring space of each of signal wires 1 and ground/power wires 2 are determined to be a wire width W1 (the minimum wire width) and a wiring space S1, respectively. A wire width and a wiring space of the via-hole neighboring region 1a or ...	12/16/2003
6656814	Methods of fabricating integrated circuit devices including distributed and isolated dummy conductive regions An integrated circuit device is fabricated by forming at least one isolation region in an area of a semiconductor substrate, such as a monolithic semiconductor substrate or a silicon on insulator (SOI) substrate. The at least one isolation region defines ...	12/02/2003
6653717	Enhancement in throughput and planarity during CMP using a dielectric stack containing an HDP oxide A semiconductor device and process for making the same are disclosed which use reticulated conductors and a width-selective planarizing interlevel dielectric (ILD) deposition process to improve planarity of an interconnect layer. Reticulated conductor 52 ...	11/25/2003
6649501	Method for forming a bit line for a semiconductor device The present invention discloses a method for forming a bit line of a semiconductor device which can easily perform a contact process of the semiconductor device, by forming parallel rows of I-shaped active regions, a plug poly and a ladder-type bit line. ...	11/18/2003
6649945	Wiring layout to weaken an electric field generated between the lines exposed to a high voltage Bit lines are arranged with minimum width and minimum space in a chip, and each bit line is given a maximum of first potential difference. The minimum space is the value which will not make a line short-circuit in a line due to dielectric strength, when t...	11/18/2003
6645842	Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method There are disclosed a semiconductor integrated circuit device, a semiconductor integrated circuit wiring method and a cell arranging method, which can reduce delay in a semiconductor integrated circuit and improve noise resistibility, achieve facility of ...	11/11/2003
6630402	Integrated circuit resistant to the formation of cracks in a passivation layer In integrated circuits produced by etching and damascene techniques, it is common for cracking to occur in dielectric material surrounding an interconnect metal layer integrated into the device, presumably as a result of the transfer of stresses from the ...	10/07/2003
6624492	Semiconductor circuit device having gate array area and method of making thereof A semiconductor integrated circuit having gate array area and IP (Intellectual Property) portion. A semiconductor integrated circuit has a lower wiring region and an upper wring region on a semiconductor substrate. A gate array region is on the semiconduc...	09/23/2003

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Class 257/E23.151 - Geometry or layout of interconnection structure (EPO)