Quotables
"I think there is a world market for maybe five computers."
Thomas Watson, chairman of IBM ; 1943
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7397106 | Laser fuse with efficient heat dissipation A semiconductor structure having an efficient thermal path and a method for forming the same are provided. The semiconductor structure includes a protection ring over a semiconductor substrate and substantially encloses a laser fuse structure. The laser fuse structu... | 07/08/2008 |
| 7378718 | Fuse element with adjustable resistance A fuse element has a first region, a second region and a third region. The first region is a portion for isolating circuitry. The second region and the third region are respectively connected to both ends of the first region and have a wider pattern width than that ... | 05/27/2008 |
| 7338843 | Method for producing an electronic component, especially a memory chip A method for producing an electronic component, especially a memory chip, using a laser-induced correction to equalize an integrated circuit by means of at least one laser via in a layer at least partially covering the circuit. The component comprises a rewiring of ... | 03/04/2008 |
| 7122850 | Semiconductor device having local interconnection layer and etch stopper pattern for preventing leakage of current A semiconductor device having a local interconnection layer and a method for manufacturing the same are provided. A local interconnection layer is formed in an interlayer dielectric (ILD) layer on an isolation layer and a junction layer, for covering a semiconductor... | 10/17/2006 |
| 7101779 | Method of forming barrier layers Mixed metal aluminum nitride and boride diffusion barriers and electrodes for integrated circuits, particularly for DRAM cell capacitors. Also provided are methods for CVD deposition of MxAlyNzBw alloy diffusion barriers, ... | 09/05/2006 |
| 6979637 | Method and structure for controlling surface properties of dielectric layers in a thin film component for improved trimming A method and structure for controlling the surface properties in the dielectric layers in a thin film component can be provided for improving the trimming process of thin film element. A metal fill is configured with a uniform fill pattern beneath an array of thin f... | 12/27/2005 |
| 6818966 | Method and structure for controlling surface properties of dielectric layers in a thin film component for improved trimming A method and structure for controlling the surface properties in the dielectric layers in a thin film component can be provided for improving the trimming process of thin film element. A metal fill is configured with a uniform fill pattern beneath an array of thin f... | 11/16/2004 |
| 6703582 | Energy-efficient method and system for processing target material using an amplified, wavelength-shifted pulse train An energy-efficient method and system for processing target material such as microstructures in a microscopic region without causing undesirable changes in electrical and/or physical characteristics of material surrounding the target material is provided.... | 03/09/2004 |
| 6703263 | Semiconductor fuses, methods of using the same, methods of making the same, and semiconductor devices containing the same Fuses for integrated circuits and semiconductor devices, methods for making the same, methods of using the same, and semiconductor devices containing the same. The semiconductor fuse contains two conductive layers--an overlying and underlying layer--on an... | 03/09/2004 |
| 6700161 | Variable resistor structure and method for forming and programming a variable resistor for electronic circuits A non-ablative structure and method for forming a variable resistor includes providing a programmable resistive element including two or more different conductive materials, and changing a resistance of the programmable resistive element to a finite value... | 03/02/2004 |
| 6693343 | Self-passivating Cu laser fuse In an integrated circuit structure, the improvement comprising a self-passivating Cu-laser fuse characterized by resistance to oxidation and corrosion and improved adhesion in the interface between Cu and metallization lines and Cu and a dielectric cap su... | 02/17/2004 |
| 6687973 | Optimized metal fuse process A metal fuse process that uses a thinner (e.g., 6000 Å) oxide (108) over the top interconnect (102). The oxide (108) is removed over the probe pads (106) for testing but is not removed over the fuses (104). Because the oxide (108) is thin at the upper co... | 02/10/2004 |
| 6686644 | Semiconductor device provided with fuse and method of disconnecting fuse A high-strength protective member made of tungsten is disposed under a disconnecting point of a fuse. This protective member is formed simultaneously with formation of a via contact portion which connects the fuse with wiring, for example.... | 02/03/2004 |
| 6686266 | Method for forming a fuse in a semiconductor device A method for forming a fuse pattern for repairing a bad cell includes forming a metal wiring pattern on a substrate and successively forming an insulating layer on the metal wiring pattern and the substrate. The insulating layer of a region for defining t... | 02/03/2004 |
| 6682959 | Architecture of laser fuse box of semiconductor integrated circuit and method for fabricating the same The invention relates to a fuse layout structure in a laser fuse box of a semiconductor integrated circuit and a method for fabricating the same. In one example of the invention, the fuse layout structure in a laser fuse box of the semiconductor integrate... | 01/27/2004 |
| 6677188 | Methods for forming a fuse in a semiconductor device According to one embodiment of the invention, a method is provided. The method includes lining, with a conductive liner, a surface of a dielectric layer. The surface defines at least two trenches separated by a platform. Each of the defined trenches inclu... | 01/13/2004 |
| 6677226 | Method for forming an integrated circuit having a bonding pad and a fuse In one embodiment, a first dielectric layer (32) that overlies a fuse (16) and a bonding pad (30) is etched with a first etch process. This first etch process exposes a portion (40) of a second dielectric layer (20) that underlies the first dielectric lay... | 01/13/2004 |
| 6677195 | Semiconductor integrated circuit device and method of producing the same A semiconductor integrated circuit device has: a layer insulating film formed on a semiconductor substrate; a fuse portion which is configured by an uppermost metal wiring layer that is formed on the layer insulating film; an inorganic insulating protecti... | 01/13/2004 |
| 6670693 | Laser synthesized wide-bandgap semiconductor electronic devices and circuits A laser apparatus and methods are disclosed for synthesizing areas of wide-bandgap semi-conductor substrates or thin films, including wide-bandgap semiconductors such as silicon carbide, aluminum nitride, gallium nitride and diamond to produce electronic ... | 12/30/2003 |
| 6667195 | Laser repair operation A method of conducting a laser repair operation. A silicon wafer has a plurality of chips thereon. Each chip has a plurality of bonding pads, a plurality of testing pads, a plurality of fuses and a passivation layer for protecting the chip. The passivatio... | 12/23/2003 |
| 6667534 | Copper fuse structure and method for manufacturing the same A copper fuse structure and the method for fabricating the same is disclosed in this present invention. By employing an inner copper metal layer as a fuse, the copper fuse according to this invention can be easily zipped with a laser repair tool. Furtherm... | 12/23/2003 |
| 6667535 | Fuse structure A novel fuse structure. An optimal position of laser spot is defined above a substrate. A first conductive layer is formed on part of the substrate. A first dielectric layer is formed on the substrate and the first conductive layer. A second conductive la... | 12/23/2003 |
| 6664141 | Method of forming metal fuses in CMOS processes with copper interconnect The present invention provides a method of forming a semiconductor device fuse and a semiconductor device fuse structure. A first dielectric layer is formed on top of a metal layer in a semiconductor device. The dielectric layer is patterned to provide ac... | 12/16/2003 |
| 6664142 | Laser repair operation A method of conducting a laser repair operation. A silicon wafer has a plurality of chips thereon. Each chip has a plurality of bonding pads, a plurality of testing pads, a plurality of fuses and a passivation layer for protecting the chip. The passivatio... | 12/16/2003 |
| 6664174 | Semiconductor device and method for fabricating the same The semiconductor device includes a blocking layer 12 formed on a substrate 10, an insulation film 14 formed on the blocking layer 12, and a fuse 22 formed on the insulation film 14. The blocking layer 12 is formed below the fuse 22, whereby the fuse is d... | 12/16/2003 |
| 6661106 | Alignment mark structure for laser fusing and method of use The present invention relates to an alignment mark structure for laser fusing. An alignment mark structure is formed which is comprised of image elements that are placed on different film layers in a semiconductor device. Alignment is accomplished by exam... | 12/09/2003 |
| 6656826 | Semiconductor device with fuse to be blown with energy beam and method of manufacturing the semiconductor device A semiconductor device has a fuse to be blown with an energy beam. The semiconductor device has copper wiring levels formed on a semiconductor substrate on which semiconductor elements are formed, an uppermost wiring level formed on said copper wiring lev... | 12/02/2003 |
| 6649997 | Semiconductor device having fuses or anti-fuses A laminated dummy pattern formed of plural metals including aluminum and tungsten is formed below a fuse or anti-fuse and an influence by application of laser energy at the time of laser blow on an wiring or element can be prevented.... | 11/18/2003 |
| 6642135 | Method for forming semiconductor memory device having a fuse A fabrication method for forming a semiconductor device having a fuse is provided. A substrate includes a cell array area, a peripheral circuit area and a global step difference between the cell array area and the peripheral circuit area. The substrate co... | 11/04/2003 |
| 6638796 | Method of forming a novel top-metal fuse structure A method of forming a top-metal fuse structure comprising the following steps. A structure having an intermetal dielectric layer is formed thereover, the structure including a fuse region and an RDL/bump/bonding pad region. A composite metal layer is form... | 10/28/2003 |
| 6639297 | Fuse structure A novel fuse structure. An optimal position of laser spol is defined above a substrate. A first conductive layer is formed on part of the substrate. A first dielectric layer is formed on the substrate and the first conductive layer. A second conductive la... | 10/28/2003 |
| 6639863 | Semiconductor integrated circuit device having link element A semiconductor integrated circuit device has a first LT fuse group for storing replacement information used in a memory array; a second LT fuse group for storing confirmation information to confirm whether the first LT fuse group has accurately stored th... | 10/28/2003 |
| 6638845 | Semiconductor device and manufacturing method of the same A semiconductor device comprises fuse elements formed on an insulating interlayer over a semiconductor substrate. A groove is formed in the insulating interlayer at each space between the fuse elements. A silicon nitride film of a predetermined thickness ... | 10/28/2003 |
| 6639177 | Method and system for processing one or more microstructures of a multi-material device A method and system for processing at least one microstructure which is part of a multi-material device containing a plurality of microstructures is provided. The at least one microstructure has a designated region for target material removal. The method ... | 10/28/2003 |
| 6632716 | Semiconductor device and manufacturing method thereof A semiconductor device is comprised of: an element isolating film formed on one major surface of a semiconductor substrate; an element forming region formed on the major surface and surrounded by the element isolating film; a gate electrode formed via a g... | 10/14/2003 |
| 6630723 | Laser programming of integrated circuits Laser Programming of Integrated Circuits. The invention relates to the laser adjustment or laser programming of laser fuses of an integrated circuit on a chip, with laser light, the integrated circuit having a plurality of laser fuses and being connected ... | 10/07/2003 |
| 6627968 | Integrated capacitor and fuse A process for forming a capacitive structure and a fuse structure in an integrated circuit device includes forming a first capacitor plate and first and second fuse electrodes in a first dielectric layer of the device. In a second dielectric layer overlyi... | 09/30/2003 |
| 6624524 | Laser alignment target A technique to form a structure with a rough topography (415) in a planarized semiconductor process. The rough topography (415) is formed by creating cored contacts (433). Subsequent process layers may be further stacked on top of the cored contacts in or... | 09/23/2003 |
| 6607945 | Laser-assisted silicide fuse programming A method is provided, the method comprising programming a silicide fuse by passing a current through the silicide fuse while substantially simultaneously irradiating the silicide fuse with a laser.... | 08/19/2003 |
| 6597055 | Redundancy structure in self-aligned contacts A fuse link redundancy structure to implement redundant circuits within an integrated circuit has an insulating layer over a conductive layer of the fuse link is sufficiently thin and transparent to allow destruction of the conductive layer by an intense ... | 07/22/2003 |
