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| Number | Title | Issue Date |
| 7432585 | Semiconductor device electronic component, circuit board, and electronic device A semiconductor device includes: a semiconductor substrate having an active face; a first electrode provided on or above the active face; an external connection terminal provided on or above the active face and electrically connected to the first electrode; and a co... | 10/07/2008 |
| 7368803 | System and method for protecting microelectromechanical systems array using back-plate with non-flat portion Disclosed is an electronic device utilizing interferometric modulation and a package of the device. The packaged device includes a substrate, an interferometric modulation display array formed on the substrate, and a back-plate. The back-plate is placed over the dis... | 05/06/2008 |
| 7291922 | Substrate with many via contact means disposed therein A substrate having many via contact means disposed therein. Each of the via contact means is composed of a via hole, as a through-hole, formed in the substrate, a metal film disposed on the inner peripheral surface of the via hole, and a solder filled into the cavit... | 11/06/2007 |
| 7271486 | Retarding agglomeration of Ni monosilicide using Ni alloys A method for providing a low resistance non-agglomerated Ni monosilicide contact that is useful in semiconductor devices. Where the inventive method of fabricating a substantially non-agglomerated Ni alloy monosilicide comprises the steps of: forming a metal alloy l... | 09/18/2007 |
| 7199458 | Stacked offset semiconductor package and method for fabricating In the stacked semiconductor package, on a first semiconductor chip, a second semiconductor chip is stacked offset such that a portion of the first semiconductor chip is exposed. At least one first conductor electrically connects the exposed portion of the first sem... | 04/03/2007 |
| 7148578 | Semiconductor multi-chip package A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is ele... | 12/12/2006 |
| 7109585 | Junction interconnection structures An integrated circuit device includes a semiconductor substrate having an interlayer insulating layer thereon and a first junction block embedded in the interlayer insulating layer. The first junction block includes a first plurality of conductive junction traces lo... | 09/19/2006 |
| 6698086 | Method for the linear configuration of metallic fuse sections on wafers Linear configurations of metallic fuse sections have a bit combination which represents a characteristic of a circuit on a wafer. The metallic fuse sections need to be rid of a polyimide layer covering them in order to make it possible to burn the fuse se... | 03/02/2004 |
| 6692995 | Physically deposited layer to electrically connect circuit edit connection targets Disclosed is a layer to electrically connect targets during a circuit edit of an integrated circuit and systems and methods for forming the layer. The layer contains a conductive material, such as gold or another metal, which has been physically deposited... | 02/17/2004 |
| 6674174 | Controlled impedance transmission lines in a redistribution layer In one embodiment, the invention includes first and second transmission lines fabricated in a redistribution layer over a semiconductor die. The first transmission line has a first distance from a first ground return path formed in a first metal level. Th... | 01/06/2004 |
| 6673707 | Method of forming semiconductor device utilizing die active surfaces for laterally extending die internal and external connections The formation of routing traces on an external surface of a semiconductor device, such as a flip-chip, which has a plurality of ball or bump sites patterned in specific locations, wherein the ball or bump sites are in electrical communication with externa... | 01/06/2004 |
| 6674168 | Single and multilevel rework A method of reworking BEOL (back end of a processing line) metallization levels of damascene metallurgy comprises forming a plurality of BEOL metallization levels over a substrate, forming line and via portions in the BEOL metallization levels, selectivel... | 01/06/2004 |
| 6670693 | Laser synthesized wide-bandgap semiconductor electronic devices and circuits A laser apparatus and methods are disclosed for synthesizing areas of wide-bandgap semi-conductor substrates or thin films, including wide-bandgap semiconductors such as silicon carbide, aluminum nitride, gallium nitride and diamond to produce electronic ... | 12/30/2003 |
| 6664176 | Method of making pad-rerouting for integrated circuit chips A method for forming printed re-routing for wafer level packaging, especially chip size packaging. The method includes forming a contact layer on a semiconductor die, printing a conductive redistribution structure on the contact layer, and etching the con... | 12/16/2003 |
| 6664632 | Utilization of die active surfaces for laterally extending die internal and external connections The formation of routing traces on an external surface of a semiconductor device, such as a flip-chip, which has a plurality of ball or bump sites patterned in specific locations, wherein the ball or bump sites are in electrical communication with externa... | 12/16/2003 |
| 6649499 | Method of varying the resistance along a conductive layer A method for varying the resistance along a conductive layer. The method including the step of removing at least a portion of a resistance-altering constituent diffused within the conductive layer.... | 11/18/2003 |
| 6649999 | Semiconductor chip configuration with a layer sequence with functional elements contacted by contact pads In a semiconductor chip, conductive tracks run in a rewiring layer from contact pads to contact elevations. The contact pads are formed as vias. The conductive tracks are constructed in sections as bottom electrodes of trimming capacitors. The top electro... | 11/18/2003 |
| 6642102 | Barrier material encapsulation of programmable material A method comprising forming as stacked materials on a substrate, a volume of programmable material and a signal line, conformably forming a first dielectric material on the stacked materials, forming a second dielectric material on the first material, etc... | 11/04/2003 |
| 6642627 | Semiconductor chip having bond pads and multi-chip package A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pat... | 11/04/2003 |
| 6633183 | Antifuse reroute of dies A circuit is provided with a programmable switching matrix incorporating at least one antifuse to selectively route signal paths. The selective routing of signal paths may be used for example, to internally reroute contact pin assignments on semiconductor... | 10/14/2003 |
| 6633196 | Device and method for limiting the extent to which circuits in integrated circuit dice electrically load bond pads and other circuit nodes in the dice An integrated circuit die includes a bond pad connected to first and second input buffers in the die through laser fuses. In one operating configuration of the die, the die uses the first input buffer but does not use the second input buffer, so the laser... | 10/14/2003 |
| 6630643 | Method and structure for forming metallic interconnections using directed thermal diffusion Energy is applied to a portion of a conducting body. In preferred embodiments, relative motion between the conducting body and the energy source is created such that the energy source moves along a thermal diffusion front, thereby enhancing the thermal di... | 10/07/2003 |
| 6627998 | Wafer scale thin film package A chip module having a chip with a flexible multilayer redistribution thin film attached thereto for connection to a substrate. The thin film acts as both a redistribution medium with multiple layers of redistribution metallurgy for chip power and signals... | 09/30/2003 |
| 6624506 | Multichip semiconductor device and memory card A plurality of semiconductor chips with the same structure are stacked to construct a multichip semiconductor device. In each of the semiconductor chips, an optional circuit is formed. In the optional circuit, fuses corresponding to the stacked-stage numb... | 09/23/2003 |
| 6614118 | Structures to mechanically stabilize isolated top-level metal lines The invention provides in one embodiment thereof an integrated circuit. The integrated circuit includes a first interconnection metallization layer formed upon a substrate. The integrated circuit further includes a second interconnection metallization lay... | 09/02/2003 |
| 6608355 | Semiconductor integrated circuit having anti-fuse, method of fabricating, and method of writing data in the same A semiconductor integrated contains a first MOS transistor of a first conductivity type formed on a surface of a semiconductor substrate, and a second MOS transistor of the first conductivity type having a drain-source breakdown voltage lower than that of... | 08/19/2003 |
| 6596563 | Method for double-layer implementation of metal options in an integrated chip for efficient silicon debug In one aspect of the present invention, a method provides a connecting path diversion through an upper layer of an integrated circuit by alteration of a connecting path through a lower layer of the integrated circuit. This method enables a circuit path in... | 07/22/2003 |
| 6593646 | Dual die memory A double-sized chip assembly and method is provided for two back-to-back integrated-circuit chips which both have the same fabrication mask sets. An electrically-selectable bonding-pad connection option alternatively provides a standard, non-reversed, opt... | 07/15/2003 |
| 6586961 | Structure and method of repair of integrated circuits The present invention relates to an integrated circuit, at least one portion of which includes at least one group of standby cells for possible connection to said portion of the integrated circuit by replacement connections, the length of which cannot exc... | 07/01/2003 |
| 6583035 | Semiconductor package with a controlled impedance bus and method of forming same An apparatus includes a first substrate having a set of semiconductor devices formed within it. The apparatus also includes a second substrate. A third substrate has a data conductor coupled between first and second connections to the second substrate. Th... | 06/24/2003 |
| 6577008 | Metal redistribution layer having solderable pads and wire bondable pads A redistribution metallization scheme combines solder bumps and wire bond pads in addition to existing bond pads to enhance the connectivity of a semiconductor device, especially in flip-chip applications. The fabrication method includes forming the addit... | 06/10/2003 |
| 6559544 | Programmable interconnect for semiconductor devices A structure for selectively programming interconnections between an input contact and an output contact segment in a multilayer semiconductor, comprising a first group of metal segments each being formed on successive layers of the semiconductor and being... | 05/06/2003 |
| 6541850 | Utilization of die active surfaces for laterally extending die internal and external connections The formation of routing traces on an external surface of a semiconductor device, such as a flip-chip, which has a plurality of ball or bump sites patterned in specific locations, wherein the ball or bump sites are in electrical communication with externa... | 04/01/2003 |
| 6531756 | Laser fuse and antifuse structures formed over the active circuitry of an integrated circuit In an integrated circuit where one desires the most compact arrangement of fuses and active circuitry, an insulating layer is deposited over active circuitry which includes the associated interconnect layers. A protective layer made with a reflective mate... | 03/11/2003 |
| 6524885 | Method, apparatus and system for building an interposer onto a semiconductor wafer using laser techniques The present invention provides a method, apparatus and system for building a wafer-interposer assembly. The method includes the steps of forming a redistribution layer (RDL) pad on a semiconductor wafer. The semiconductor wafer has a semiconductor die and... | 02/25/2003 |
| 6511901 | Metal redistribution layer having solderable pads and wire bondable pads A redistribution metallization scheme combines solder bumps and wire bond pads in addition to existing bond pads to enhance the connectivity of a semiconductor device, especially in flip-chip applications. The fabrication method includes forming the addit... | 01/28/2003 |
| 6472745 | Semiconductor device A semiconductor device in which a plurality of semiconductor chips are consolidated into one and which is provided with at least a set of rerouting wiring lines formed so as to interconnect electrodes of the respective semiconductor chips, the electrodes ... | 10/29/2002 |
| 6458676 | Method of varying the resistance along a conductive layer A method for varying the resistance along a conductive layer. The method including the step of removing at least a portion of a resistance-altering constituent diffused within the conductive layer.... | 10/01/2002 |
| 6459136 | Single metal programmability in a customizable integrated circuit device A customizable integrated circuit including a plurality of electrically conducting routing layers formed on a substrate for interconnecting a plurality of logic units formed on the substrate, including a first routing layer including a plurality of elonga... | 10/01/2002 |
| 6429495 | Semiconductor device with address programming circuit To provide an address programming device free from laser-blowing, a first, thin gate oxide film is formed on a semiconductor substrate, a first gate electrode is formed thereon, a second, thick gate oxide film is formed thereon, and a second gate electrod... | 08/06/2002 |
