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| Number | Title | Issue Date |
| 7442969 | Top layers of metal for high performance IC's A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an ... | 10/28/2008 |
| 7439628 | Method for improved process latitude by elongated via integration Interconnect dual damascene structure are fabricated by depositing on a layer of at least one dielectric, a mask forming layer for providing the via-level mask layer of the dual damascene structures; creating an elongated via pattern in the via-level mask layer; dep... | 10/21/2008 |
| 7439623 | Semiconductor device having via connecting between interconnects A first insulating film is provided between a lower interconnect and an upper interconnect. The lower interconnect and the upper interconnect are connected to each other by way of a via formed in the first insulating film. A dummy via or an insulating slit is formed... | 10/21/2008 |
| 7435618 | Method to manufacture a coreless packaging substrate A method for manufacturing a coreless packaging substrate is disclosed. The method can produce a coreless packaging substrate which comprises: at least a built-up structure having a first solder mask and a second solder mask, wherein a plurality of openings are form... | 10/14/2008 |
| 7432597 | Semiconductor device and method of manufacturing the same In a semiconductor device including a memory region and a logic region, one or more of a plurality of logic transistor connection plugs, buried in a first insulating layer and connected to a diffusion layer of a logic transistor, are left unconnected to a first inte... | 10/07/2008 |
| 7432598 | Semiconductor device A semiconductor device capable of reducing electrical leakage generated when a contact hole is misaligned and a manufacturing method thereof is disclosed. The semiconductor device includes three conductive layers with various and different portions overlapping each ... | 10/07/2008 |
| 7427803 | Electromagnetic shielding using through-silicon vias An isolation structure for electromagnetic interference includes a semiconductor substrate, a first integrated circuit in the semiconductor substrate, a second integrated circuit in the semiconductor substrate, and an isolation structure in a direct path between the... | 09/23/2008 |
| 7425753 | Semiconductor device A semiconductor device equipped with an integrated circuit including a metal thin-film-resistor object is disclosed. The semiconductor device includes a lower layer side insulator film formed on a semiconductor substrate, a metal wiring pattern formed on the lower l... | 09/16/2008 |
| 7422979 | Method of forming a semiconductor device having a diffusion barrier stack and structure thereof A diffusion barrier stack is formed by forming a layer comprising a metal over a conductor that includes copper; and forming a first dielectric layer over the layer, wherein the dielectric layer is of a thickness that alone it can not serve as a diffusion barrier la... | 09/09/2008 |
| 7419850 | Method to manufacture a coreless packaging substrate A method of manufacturing a coreless packaging substrate is disclosed. The method can produce a coreless packaging substrate which comprises: at least a built-up structure having a first solder mask and a second solder mask, wherein a plurality of openings are forme... | 09/02/2008 |
| 7416982 | Semiconductor devices and methods for manufacturing the same Semiconductor devices having a copper line layer and methods for manufacturing the same are disclosed. An illustrated semiconductor device comprises a damascene insulating layer having a contact hole, a barrier metal layer including a first ruthenium layer, a ruthen... | 08/26/2008 |
| 7414275 | Multi-level interconnections for an integrated circuit chip Multilevel metallization layouts for an integrated circuit chip including transistors having first, second and third elements to which metallization layouts connect. The layouts minimize current limiting mechanism including electromigration by positioning the connec... | 08/19/2008 |
| 7405109 | Method of fabricating the routing of electrical signals A method for manufacturing a layered structure for routing electrical signals comprising the steps of providing a layout for the layered structure having an insulating layer with at least one signal trace, a via, and a stub trace on a first side of the insulating la... | 07/29/2008 |
| 7405473 | Techniques for optimizing electrical performance and layout efficiency in connectors with via placement and routing Techniques are provided for placing and routing vias that conduct signals through a connector between two electrical units. Vias that conduct a first set of signals are placed next to vias that provide return paths for the first set of signals to reduce cross-talk o... | 07/29/2008 |
| 7402883 | Back end of the line structures with liner and noble metal layer A back end of the line (BEOL) structure of a semiconductor device is presented. In one embodiment, the structure may include a first liner layer disposed on an intermediate interconnect structure, the intermediate interconnect structure having an opening disposed be... | 07/22/2008 |
| 7397125 | Semiconductor device with bonding pad support structure A semiconductor device having bonding pads on a semiconductor substrate includes: an upper copper layer that is formed on the lower surface of the bonding pads with a barrier metal interposed and that has a copper area ratio that is greater than layers in which circ... | 07/08/2008 |
| 7394134 | Semiconductor device with electrostatic discharge protection A semiconductor device is provided having a high performance resistance element. In an N-type well isolated by an insulating film, two higher concentration N-type regions are formed. An interlayer insulating film is also formed. In a plurality of openings in the int... | 07/01/2008 |
| 7394155 | Top and sidewall bridged interconnect structure and method An interconnect structure and its method for fabrication each employ an interconnect formed over and adjacent an active region of a semiconductor substrate. A gate electrode is also formed over the active region. Spacer layers are formed adjoining the interconnect a... | 07/01/2008 |
| 7391115 | Semiconductor device and manufacturing method thereof An object of the present invention is to provide a semiconductor device which comprises a barrier film having a high etching selection ratio of the interlayer insulating film thereto, a good preventive function against the Cu diffusion, a low dielectric constant and... | 06/24/2008 |
| 7388240 | Non-volatile memory device capable of preventing damage by plasma charge A non-volatile memory device for preventing damage by plasma charges includes a gate electrode formed on a predetermined region of a semiconductor substrate, a source/drain region which is overlapped with the gate electrode and formed in a first well region of the s... | 06/17/2008 |
| 7388224 | Structure for determining thermal cycle reliability A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is ... | 06/17/2008 |
| 7382054 | Method for forming self-aligned contacts and local interconnects simultaneously The present invention relates generally to semiconductors, and more specifically to semiconductor memory device structures and an improved fabrication process for making the same. The improved fabrication process allows the self-aligned contacts and local interconne... | 06/03/2008 |
| 7382053 | Power supply wiring structure Provided is a power supply wiring structure which comprises a first and a second power supply wirings, which are disposed on different planes to cross each other two-dimensionally. The first and second power supply wirings are interlayer-connected by a first via at ... | 06/03/2008 |
| 7378740 | Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit An improved dual damascene structure is provided for use in the wiring-line structures of multi-level interconnects in integrated circuit. In this dual damascene structure, low-K (low dielectric constant) dielectric materials are used to form both the di-electric la... | 05/27/2008 |
| 7378340 | Method of manufacturing semiconductor device and semiconductor device The present invention provides a method of manufacturing a semiconductor device and a semiconductor device that allow use of interlayer and interconnect insulating films having a low dielectric constant in forming a dual damascene structure. A first insulating film,... | 05/27/2008 |
| 7375423 | Semiconductor device A semiconductor device includes a pad composed of plural wiring layers and a power supply ring to provide a power supply provided through the pad for the power supply to an internal circuit, and the pad for the power supply and the power supply ring are connected by... | 05/20/2008 |
| 7368804 | Method and apparatus of stress relief in semiconductor structures A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad a... | 05/06/2008 |
| 7361991 | Closed air gap interconnect structure A closed air gap interconnect structure is described. The structure includes discrete regions of a permanent support dielectric under the interconnect lines so that the lines are substantially surrounded by air except for the discrete regions of the support dielectr... | 04/22/2008 |
| 7348672 | Interconnects with improved reliability An interconnect architecture with improved reliability. An interconnect with rounded top corners is inlaid in a dielectric layer. A filler borders the interconnect along the corners of the interconnect. ... | 03/25/2008 |
| 7348675 | Microcircuit fabrication and interconnection Embodiments of methods in accordance with the present invention provide three-dimensional carbon nanotube (CNT) integrated circuits comprising layers of arrays of CNT's separated by dielectric layers with conductive traces formed within the dielectric layers to elec... | 03/25/2008 |
| 7339272 | Semiconductor device with scattering bars adjacent conductive lines A semiconductor device and method of manufacture thereof wherein scattering bars are disposed on both sides of an isolated conductive line of a semiconductor device to improve the lithography results. The scattering bars have a sufficient width and are spaced a suff... | 03/04/2008 |
| 7332753 | Semiconductor device, wafer and method of designing and manufacturing the same A process margin of an interconnect is to be expanded, to minimize the impact of vibration generated during a scanning motion of a scanning type exposure equipment. In a semiconductor device, the interconnect handling a greater amount of data (frequently used interc... | 02/19/2008 |
| 7332812 | Memory card with connecting portions for connection to an adapter Semiconductor devices having conductive lines with extended ends and methods of extending conductive line ends by a variable distance are disclosed. An end of a first conductive feature of an interconnect structure is extended by a first distance, and an end of a se... | 02/19/2008 |
| 7332805 | Electronic package with improved current carrying capability and method of forming the same An electronic package and method for forming such package that expands the current capability of lines and/or reducing line resistance for packages with a given feature dimension while relaxing feature tolerances. The methods and structures include electrical wiring... | 02/19/2008 |
| 7332449 | Method for forming dual damascenes with supercritical fluid treatments A method for forming a damascene structure by providing a single process solution for resist ashing while avoiding and repairing plasma etching damage as well as removing absorbed moisture in the dielectric layer, the method including providing a substrate comprisin... | 02/19/2008 |
| 7326993 | Nonvolatile semiconductor memory and method for fabricating the same A nonvolatile semiconductor memory includes a first semiconductor layer; second semiconductor regions formed on the first semiconductor layer having device isolating regions extended in a column direction; a first interlayer insulator film formed above the first sem... | 02/05/2008 |
| 7323784 | Top via pattern for bond pad structure Top via pattern for a bond pad structure has at least one first via group and at least one second via group adjacent to each other. The first via group has at least two line vias extending in a first direction. The second via group has at least two line vias extendi... | 01/29/2008 |
| 7319067 | Method of simultaneously controlling ADI-AEI CD differences of openings having different sizes and etching process utilizing the same method A method of simultaneously controlling the ADI-AEI CD differences of openings having different sizes is disclosed. The openings are formed by: forming an ARC and a photoresist layer with a first and a second opening patterns of different sizes therein on a material ... | 01/15/2008 |
| 7317255 | Reliable printed wiring board assembly employing packages with solder joints An exemplary assembly comprises a printed wiring board having a first surface, and a package including a plurality of solder joints, such as solder balls, on one surface of the package. An anchor via is defined through the first surface of the printed wiring board, ... | 01/08/2008 |
| 7309917 | Multilayer board and a semiconductor device Preparing a bottom grounding layer eliminates grounding pins, thereby the number of signal pins can be increased in a multilayer board that includes a grounding layer, a signal layer, a power supply layer, a grounding via, a signal via, a power supply via and the li... | 12/18/2007 |
