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| Number | Title | Issue Date |
| 7425501 | Semiconductor structure implementing sacrificial material and methods for making and implementing the same A method for making a semiconductor device is provided. The method includes forming transistor structures on a substrate and forming interconnect metallization structures in a plurality of levels through depositing a sacrificial layer. A dual damascene process is pe... | 09/16/2008 |
| 7414275 | Multi-level interconnections for an integrated circuit chip Multilevel metallization layouts for an integrated circuit chip including transistors having first, second and third elements to which metallization layouts connect. The layouts minimize current limiting mechanism including electromigration by positioning the connec... | 08/19/2008 |
| 7402883 | Back end of the line structures with liner and noble metal layer A back end of the line (BEOL) structure of a semiconductor device is presented. In one embodiment, the structure may include a first liner layer disposed on an intermediate interconnect structure, the intermediate interconnect structure having an opening disposed be... | 07/22/2008 |
| 7400008 | Semiconductor device and manufacturing process therefor An objective of this invention is to provide a semiconductor device comprising a less bias-dependent capacitative element with a large capacity per a unit area, having a configuration which can be manufactured using an existing structure in a semiconductor device. T... | 07/15/2008 |
| 7378340 | Method of manufacturing semiconductor device and semiconductor device The present invention provides a method of manufacturing a semiconductor device and a semiconductor device that allow use of interlayer and interconnect insulating films having a low dielectric constant in forming a dual damascene structure. A first insulating film,... | 05/27/2008 |
| 7372153 | Integrated circuit package bond pad having plurality of conductive members An integrated circuit package bond pad includes an insulating layer and an electrode located over the insulating layer. The electrode has a first surface configured to be bonded to external circuitry and a second surface opposite the first surface. A plurality of co... | 05/13/2008 |
| 7361991 | Closed air gap interconnect structure A closed air gap interconnect structure is described. The structure includes discrete regions of a permanent support dielectric under the interconnect lines so that the lines are substantially surrounded by air except for the discrete regions of the support dielectr... | 04/22/2008 |
| 7352059 | Low loss interconnect structure for use in microelectronic circuits A low loss on-die interconnect structure includes first and second differential signal lines on one of the metal layers of a microelectronic die. One or more traces may also be provided on another metal layer of the die that are non-parallel (e.g., orthogonal) to th... | 04/01/2008 |
| 7351656 | Semiconductor device having oxidized metal film and manufacture method of the same A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in ... | 04/01/2008 |
| 7327030 | Apparatus and method incorporating discrete passive components in an electronic package An apparatus and method for incorporating discrete passive components into an integrated circuit package. A metal layer is formed over a surface of a substrate. A layer of photosensitive material is then formed over the metal layer. Using standard photolithographic ... | 02/05/2008 |
| 7326987 | Non-continuous encapsulation layer for MIM capacitor The present invention relates to metal-insulator-metal (MIM) capacitors and field effect transistors (FETs) formed on a semiconductor substrate. The FETs are formed in Front End of Line (FEOL) levels below the MIM capacitors which are formed in upper Back End of Lin... | 02/05/2008 |
| 7291923 | Tapered signal lines In an integrated circuit, a layer including a plurality of conductive wires is described. A first wire, having sidewalls, is tapered from a proximal end which has a first width to a distal end which has a second width, to reduce width from the first width to the sec... | 11/06/2007 |
| 7285860 | Method and structure for defect monitoring of semiconductor devices using power bus wiring grids A method for implementing defect inspection of an integrated circuit includes configuring a power bus grid structure on a first metal interconnect level, the power bus grid structure including a first plurality of wire pairs. The first plurality of wire pairs is arr... | 10/23/2007 |
| 7282803 | Integrated electronic circuit comprising a capacitor and a planar interference inhibiting metallic screen An electronic circuit includes a substrate. A capacitor and at least one semiconductor component are supported by a surface of the substrate. A substantially planar screen, oriented parallel to the surface of the substrate and made of metallic material, is placed be... | 10/16/2007 |
| 7276776 | Semiconductor device A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnec... | 10/02/2007 |
| 7271488 | Semiconductor integrated circuit A semiconductor integrated circuit having a plurality of interconnect layers and at least one via connecting interconnects of two adjacent interconnect layers, wherein each interconnect layer has a plurality of first interconnect groups and second interconnect group... | 09/18/2007 |
| 7265448 | Interconnect structure for power transistors An integrated circuit according to the present invention includes first, second and third plane-like metal layers. A first transistor has a first control terminal and first and second terminals. The second terminal communicates with the first plane-like metal layer.... | 09/04/2007 |
| 7244999 | Capacitor applicable to a device requiring large capacitance A capacitor includes a first electrode and a second electrode arranged so that a main surface of the first electrode opposes a main surface of the second electrode, a first pseudo electrode layer disposed on the main surface of the first electrode, and a dielectric ... | 07/17/2007 |
| 7242073 | Capacitor having an anodic metal oxide substrate In one embodiment, a structure and method including an anodic metal oxide substrate used to form a capacitor are described herein. ... | 07/10/2007 |
| 7230338 | Semiconductor device that improves electrical connection reliability A semiconductor device including: a semiconductor section in which an element is formed; an insulating layer formed on the semiconductor section; an electrode pad formed on the insulating layer; a contact section formed of a conductive material provided in a contact... | 06/12/2007 |
| 7230337 | Semiconductor device including ladder-shaped siloxane hydride and method for manufacturing same The present invention reduces the effective dielectric constant of the interlayer insulating film while inhibiting the decrease of the reliability of the semiconductor device, which otherwise is caused by a moisture absorption. A copper interconnect comprising a Cu ... | 06/12/2007 |
| 7224064 | Semiconductor device having conductive interconnections and porous and nonporous insulating portions A semiconductor device and manufacturing method, wherein the semiconductor device has a semiconductor substrate on which a plurality of elements constituting a logic type device have been formed; a first interlayer insulating film on the semiconductor substrate; a p... | 05/29/2007 |
| 7180191 | Semiconductor device and method of manufacturing a semiconductor device A semiconductor device 200 comprises a SiCN film 202 formed on a semiconductor substrate (not shown), a first SiOC film 204 formed thereon, a SiCN film 208 formed thereon, a second SiOC film 210 formed thereon, a SiO2 fi... | 02/20/2007 |
| 7148535 | Zero capacitance bondpad utilizing active negative capacitance The present invention is an apparatus and system for reducing bondpad capacitance of an integrated circuit. Circuitry of the present invention may produce a negative capacitance approximately equal in magnitude to the capacitance associated with the bondpad and ther... | 12/12/2006 |
| 7129571 | Semiconductor chip package having decoupling capacitor and manufacturing method thereof A semiconductor chip package has a substrate that includes circuit lines provided on first and/or second surfaces, a power plane provided on the second surface, bump lands provided on the second surface and coupled to the circuit lines, and ball lands provided on th... | 10/31/2006 |
| 7122878 | Method to fabricate high reliable metal capacitor within copper back-end process A new method is provided for the creation of a high-reliability metal capacitor as part of back-end processing. A first layer of metal interconnect is created, ac contact point is provided in the surface of the first layer of interconnect aligned with which a capaci... | 10/17/2006 |
| 7122877 | Semiconductor device and method for producing the same A semiconductor device of the present invention includes a semiconductor substrate including an active region and an isolating region provided so as to enclose the active region; a capacitance insulating film that is provided on the active region and is in contact w... | 10/17/2006 |
| 7091617 | Design and layout techniques for low parasitic capacitance in analog circuit applications A semiconductor device that reduces the parasitic capacitance between a conductive trace and a substrate, and a method of fabricating the same. The semiconductor device includes a substrate, an insulator layer disposed upon the substrate, a conductive trace disposed... | 08/15/2006 |
| 7091615 | Concentration graded carbon doped oxide A process for forming an interlayer dielectric layer is disclosed. The method comprises first forming a carbon-doped oxide (CDO) layer with a first concentration of carbon dopants therein. Next, the CDO layer is further formed with a second concentration of carbon d... | 08/15/2006 |
| 7088003 | Structures and methods for integration of ultralow-k dielectrics with improved reliability An improved back end of the line (BEOL) interconnect structure comprising an ultralow k (ULK) dielectric is provided. The structure may be of the single or dual damascene type and comprises a dense thin dielectric layer (TDL) between a metal barrier layer and the UL... | 08/08/2006 |
| 6696760 | Semiconductor structure The present invention discloses a method of providing a substrate, the substrate having a first metal line and a second metal line isolated horizontally by a dielectric; forming an etch stop layer over the substrate; reducing thickness of the etch stop la... | 02/24/2004 |
| 6696359 | Design layout method for metal lines of an integrated circuit A process to enhance metal line layout designs is provided and includes two separate control spaces to address capacitive issues along speed sensitive pathways in an integrated circuit structure without negatively impacting the Werner Fill process. One co... | 02/24/2004 |
| 6696315 | Semiconductor device configuration with cavities of submicrometer dimensions and method of fabricating structured cavities Cavities of submicron dimension are in a cavity layer of a semiconductor device. For that purpose, processing material is deposited on ridges of a working layer that is structured from ridges and trenches. The processing material is polymerized and the po... | 02/24/2004 |
| 6693355 | Method of manufacturing a semiconductor device with an air gap formed using a photosensitive material A semiconductor structure (10) has one or more air gaps (44, 46) formed on a same layer with an interlevel dielectric (ILD) (30) using a common dielectric material (16) that is photosensitive. Additional ILDs (124, 162) may be formed on the layer. The pho... | 02/17/2004 |
| 6686643 | Substrate with at least two metal structures deposited thereon, and method for fabricating the same Metal structures that can be produced by a damascene process are disposed in a first insulating layer and a second insulating layer is disposed above the latter. There is in each case at least one cavity which is disposed between the metal structures, is ... | 02/03/2004 |
| 6682969 | Top electrode in a strongly oxidizing environment An improved charge storing device and methods for providing the same, the charge storing device comprising a conductor-insulator-conductor (CIC) sandwich. The CIC sandwich comprises a first conducting layer deposited on a semiconductor integrated circuit.... | 01/27/2004 |
| 6680541 | Semiconductor device and process for producing the same An intermetal insulating film containing at least silicon atoms, oxygen atoms and carbon atoms with the number ratio of oxygen atom to silicon atom being 1.5 or more and the number ratio of carbon atom to silicon atom being 1 to 2, and having a film thick... | 01/20/2004 |
| 6674167 | Multilevel copper interconnect with double passivation Structures, systems and methods are provide for multilevel wiring interconnects in an integrated circuit assembly which alleviate problems associated with integrated circuit size and performance. The structures, systems and methods of the present inventio... | 01/06/2004 |
| 6670022 | Nanoporous dielectric films with graded density and process for making such films The present invention relates to nanoporous dielectric films and to a process for their manufacture. A substrate having a plurality of raised lines on its surface is provided with a relatively high porosity, low dielectric constant, silicon containing pol... | 12/30/2003 |
| 6670719 | Microelectronic device package filled with liquid or pressurized gas and associated method of manufacture A microelectronic device package and method for manufacture. In one embodiment, the device package can include a microelectronic substrate having first and second device features, a conductive link that includes a conductive material extending between the... | 12/30/2003 |
