Class 257/E23.142 - Including external interconnections consisting of multilayer structure of conductive and insulating layers inseparably formed on semiconductor body (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E23.141. This subclass
No. of patents: 260
Last issue date: 10/28/2008

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Number	Title	Issue Date
7443020	Minimizing number of masks to be changed when changing existing connectivity in an integrated circuit Dummy stacks, each providing a common point of connectivity potentially across all metal layers, are incorporated along with the functional block in an integrated circuit. When the connectivity of elements of the functional block need to be changed later, the dummy ...	10/28/2008
7432556	Semiconductor device with dummy conductors At least a laminate of a gate insulating film 6 and a gate electrode 7 and an active region 13 are formed on a silicon substrate 1, and an underlying interlayer insulating film 10 is further formed. Then, a conductor 11a ...	10/07/2008
7432597	Semiconductor device and method of manufacturing the same In a semiconductor device including a memory region and a logic region, one or more of a plurality of logic transistor connection plugs, buried in a first insulating layer and connected to a diffusion layer of a logic transistor, are left unconnected to a first inte...	10/07/2008
7414275	Multi-level interconnections for an integrated circuit chip Multilevel metallization layouts for an integrated circuit chip including transistors having first, second and third elements to which metallization layouts connect. The layouts minimize current limiting mechanism including electromigration by positioning the connec...	08/19/2008
7378340	Method of manufacturing semiconductor device and semiconductor device The present invention provides a method of manufacturing a semiconductor device and a semiconductor device that allow use of interlayer and interconnect insulating films having a low dielectric constant in forming a dual damascene structure. A first insulating film,...	05/27/2008
7358548	Semiconductor integrated circuit having layout in which buffers or protection circuits are arranged in concentrated manner Buffers are arranged in a concentrated manner in a region distant from pads. The region refers to a region in a main region of a semiconductor integrated circuit, except for a central processing unit, a non-volatile memory and a volatile memory. As the buffer requir...	04/15/2008
7348674	Low capacitance wiring layout Integrated circuits having multi-level wiring layouts designed to inhibit the capacitive-resistance effect, and a method for fabricating such integrated circuits, is described. The integrated circuits have at least two planes of wiring adjacent to each other and ext...	03/25/2008
7332753	Semiconductor device, wafer and method of designing and manufacturing the same A process margin of an interconnect is to be expanded, to minimize the impact of vibration generated during a scanning motion of a scanning type exposure equipment. In a semiconductor device, the interconnect handling a greater amount of data (frequently used interc...	02/19/2008
7327024	Power module, and phase leg assembly A power module includes a substrate that includes an upper layer, an electrical insulator and a thermal coupling layer. The upper layer includes an electrically conductive pattern and is configured for receiving power devices. The electrical insulator is disposed be...	02/05/2008
7301231	Reinforced bond pad for a semiconductor device Disclosed herein are novel support structures for pad reinforcement in conjunction with new bond pad designs for semiconductor devices. The new bond pad designs avoid the problems associated with probe testing by providing a probe region that is separate from a wire...	11/27/2007
7301241	Semiconductor device for preventing defective filling of interconnection and cracking of insulating film The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42	11/27/2007
7274085	Capacitor structure A capacitor structure has a plurality of stacked conductive patterns, and each conductive pattern has a closed conductive ring, a plurality of major conductive bars arranged in parallel and electrically to the closed conductive ring, and a plurality of minor conduct...	09/25/2007
7253525	Semiconductor device including contact holes between adjacent conductor patterns and method for fabricating the same The semiconductor device comprises a semiconductor substrate 10, a conducting film 20 formed on the semiconductor substrate 10 and including two conductor patterns adjacent to each other; an etching stopper film covering the upper surface of the...	08/07/2007
7247552	Integrated circuit having structural support for a flip-chip interconnect pad and method therefor A technique for alleviating the problems of defects caused by stress applied to bond pads (32) includes, prior to actually making an integrated circuit (10), adding dummy metal lines (74, 76) to interconnect layers (18, 22, 26) to increas...	07/24/2007
7247944	Connector assembly An apparatus and method for attaching a semiconductor die to a lead frame wherein the electric contact points of the semiconductor die are relocated to the periphery of the semiconductor die through a plurality of conductive traces. A plurality of leads extends from...	07/24/2007
7245016	Circuit layout structure A circuit layout structure for a chip is provided. The chip has a bonding pad area, a nearby device area, and a substrate. The circuit layout structure essentially comprises a plurality of circuit layers, a plurality of dielectric layers and a plurality of vias. The...	07/17/2007
7239002	Integrated circuit device In a temperature sensor section of a semiconductor integrated circuit device, first vias of tungsten are formed at the topmost layer of a multi-layer wiring layer and pads of titanium are provided on regions of the multi-layer wiring layer which covers the vias. An ...	07/03/2007
7224063	Dual-damascene metallization interconnection An interconnect structure, comprising: a lower level wire having a side and a bottom, the lower level wire comprising: a lower core conductor and a lower conductive liner, the lower conductive liner on the side and the bottom of the lower level wire; an upper level ...	05/29/2007
7199458	Stacked offset semiconductor package and method for fabricating In the stacked semiconductor package, on a first semiconductor chip, a second semiconductor chip is stacked offset such that a portion of the first semiconductor chip is exposed. At least one first conductor electrically connects the exposed portion of the first sem...	04/03/2007
7190078	Interlocking via for package via integrity A method of forming an interconnection structure in a microelectronic package, and an interconnection structure of a microelectronic package formed according to the method. The method includes: providing a combination including a first conductive layer and a dielect...	03/13/2007
7187015	High-density metal capacitor using dual-damascene copper interconnect An electronic structure having a first conductive layer provided by a dual damascene fabrication process; an etch-stop layer provided by the fabrication process, and electrically coupled with the first conductive layer, the etch-stop layer having a preselected diele...	03/06/2007
7141882	Semiconductor wafer device having separated conductive patterns in peripheral area and its manufacture method A method of manufacturing a semiconductor wafer device, including the steps of: (a) forming lower wiring patterns over a semiconductor wafer, the lower wiring patterns being connected to semiconductor elements in a circuit area; (b) forming an interlevel insulating ...	11/28/2006
7132752	Semiconductor chip and semiconductor device including lamination of semiconductor chips To prevent short-circuit due to contact of bonding wires each other and to make a semiconductor device compact. A semiconductor chip with a rectangular main surface may comprise: a first side composing the main surface; a second side opposed to the first side; a mai...	11/07/2006
7112866	Method to form a cross network of air gaps within IMD layer The invention provides a new multilevel interconnect structure of air gaps in a layer of IMD. A first layer of dielectric is provided over a surface; the surface contains metal points of contact. Trenches are provided in this first layer of dielectric. The trenches ...	09/26/2006
7078729	Semiconductor device and method of manufacturing the same A semiconductor device includes a substrate, and a semiconductor thin film bonded to the substrate, wherein the semiconductor thin film includes a plurality of discrete operating regions and an element isolating region which isolates the plurality of discrete operat...	07/18/2006
6798039	Integrated circuit inductors having high quality factors Integrated circuit inductors achieve high quality factors by replacing a single conductive strand having a first cross-sectional area with a plurality of conductive strands having a combined second cross-sectional area that is smaller than the first cross-sectional ...	09/28/2004
6703666	Thin film resistor device and a method of manufacture therefor The present invention provides a thin film resistor and method of manufacture therefor. The thin film resistor comprises a resistive layer located on a first dielectric layer, first and second contact pads located on the resistive layer, and a second diel...	03/09/2004
6700205	Semiconductor devices having contact plugs and local interconnects Provided is, for example, a method for the fabrication of electrical interconnects in semiconductor devices wherein a substrate including two or more transistors having gate regions wherein the gate regions are not exposed (e.g., the gate regions are comp...	03/02/2004
6693357	Methods and semiconductor devices with wiring layer fill structures to improve planarization uniformity Semiconductor devices and manufacturing methods therefor are disclosed, in which conductive fill structures are provided in fill regions in an interconnect wiring layer between conductive wiring structures to facilitate planarization uniformity during met...	02/17/2004
6664863	LC oscillator An LC oscillator capable of oscillating even if it is fabricated on a substrate comprises a transistor, capacitor, and an inductor element 30. The inductor element 30 has two spiral conductors 120, 122 having substantially the same shape and formed on a s...	12/16/2003
6661691	Interconnection structure and methods Interconnection structures for integrated circuits have a first array of cells, at least a second array of cells parallel to the first array, and interconnections disposed for connecting cells of the first array with cells of the second array, at least so...	12/09/2003
6657310	Top layers of metal for high performance IC's A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or pol...	12/02/2003
6657309	Semiconductor chip and semiconductor device of chip-on-chip structure A semiconductor chip having a semiconductor substrate; a surface protective film covering the semiconductor substrate; and an interconnection having a portion exposed on the surface protective film, at least the exposed portion of the interconnection bein...	12/02/2003
6650000	Apparatus and method for forming a battery in an integrated circuit A method and structure that provides a battery within an integrated circuit for providing voltage to low-current electronic devices that exist within the integrated circuit. The method includes Front-End-Of-Line (FEOL) processing for generating a layer of...	11/18/2003
6645844	Methods for high density direct connect LOC assembly An apparatus and method for attaching a semiconductor die to a lead frame wherein the electric contact points of the semiconductor die are relocated to the periphery of the semiconductor die through a plurality of conductive traces. A plurality of leads e...	11/11/2003
6627926	Method of designing and structure for visual and electrical test of semiconductor devices In a semiconductor device using fill shape patterns incorporated into wiring levels to increase the planarity of the wiring levels, the fill shapes are aligned from one wiring level to another wiring level to provide lines of sight to lower wiring levels ...	09/30/2003
6624515	Microelectronic die including low RC under-layer interconnects A microelectronic die comprises a first area, a second area and an under-layer of conductive material formed in the second area to interconnect components. A method of making a microelectronic die comprises forming a layer of insulative material on a subs...	09/23/2003
6617252	Monolithic low dielectric constant platform for passive components and method A method for forming a low dielectric constant insulator in a monolithic substrate and the dielectric formed by the method. The method includes formation and patterning of a mask on a silicon substrate followed by anisotropic etching of the silicon to pro...	09/09/2003
6617669	Multilayer semiconductor wiring structure with reduced alignment mark area When the through holes are formed in the first to the eighth insulation layers, an alignment is performed by using an alignment mark provided in the lowermost wiring layer. The alignment marks provided in the insulation layers are formed by being alternat...	09/09/2003
6614118	Structures to mechanically stabilize isolated top-level metal lines The invention provides in one embodiment thereof an integrated circuit. The integrated circuit includes a first interconnection metallization layer formed upon a substrate. The integrated circuit further includes a second interconnection metallization lay...	09/02/2003

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Class 257/E23.142 - Including external interconnections consisting of multilayer structure of conductive and insulating layers inseparably formed on semiconductor body (EPO)