Celebrity Inventors
Comic actor Danny Kaye received patent D166,807 for the co-design of "Blowout Toy or the Like". It's similar to one of those toys that unravels when you blow into at a birthday party except Kaye's has three blowouts going in different directions, not just one.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7442653 | Inter-metal dielectric of semiconductor device and manufacturing method thereof including plasma treating a plasma enhanced fluorosilicate glass An exemplary manufacturing method of an inter-metal dielectric of a semiconductor device according to an embodiment of the present invention includes forming a first silicon-rich oxide (SRO) layer on a silicon substrate provided with or otherwise having a copper lin... | 10/28/2008 |
| 7397125 | Semiconductor device with bonding pad support structure A semiconductor device having bonding pads on a semiconductor substrate includes: an upper copper layer that is formed on the lower surface of the bonding pads with a barrier metal interposed and that has a copper area ratio that is greater than layers in which circ... | 07/08/2008 |
| 7381657 | Biased pulse DC reactive sputtering of oxide films A biased pulse DC reactor for sputtering of oxide films is presented. The biased pulse DC reactor couples pulsed DC at a particular frequency to the target through a filter which filters out the effects of a bias power applied to the substrate, protecting the pulsed... | 06/03/2008 |
| 7341935 | Alternative interconnect structure for semiconductor devices A semiconductor interconnect structure includes an organic and/or photosensitive etch buffer layer disposed over a contact surface. The structure further provides an interlevel dielectric formed over the etch buffer layer. A method for forming an interconnect struct... | 03/11/2008 |
| 7323423 | Forming high-k dielectric layers on smooth substrates A buffer layer and a high-k metal oxide dielectric may be formed over a smooth silicon substrate. The substrate smoothness may reduce column growth of the high-k metal oxide gate dielectric. The surface of the substrate may be saturated with hydroxyl terminations pr... | 01/29/2008 |
| 7282438 | Low-k SiC copper diffusion barrier films Copper diffusion barrier films having low dielectric constants are suitable for a variety of copper/inter-metal dielectric integration schemes. Copper diffusion barrier films in accordance with the invention are composed of one or more layers of silicon carbide, at ... | 10/16/2007 |
| 7268035 | Methods of forming semiconductor constructions comprising cerium oxide and titanium oxide The invention includes semiconductor constructions comprising dielectric materials which contain cerium oxide and titanium oxide. The dielectric materials can contain a homogeneous distribution of cerium oxide and titanium oxide, and/or can contain a laminate of cer... | 09/11/2007 |
| 7262118 | Method for generating a structure on a substrate The invention relates to a method for generating very short gate structures. In a method for generating a structure on a substrate in accordance with one embodiment of the invention, first of all a layer sequence of a first oxide layer, a first nitride layer and a s... | 08/28/2007 |
| 7192894 | High performance CMOS transistors using PMD liner stress A silicon nitride layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nit... | 03/20/2007 |
| 6696317 | Method of manufacturing a flip-chip semiconductor device with a stress-absorbing layer made of thermosetting resin In a flip-chip type semiconductor device, a plurality of pad electrodes are formed on a semiconductor substrate. An insulating stress-absorbing resin layer made of thermosetting resin is adhered to the substrate as a composite layer in conjunction with a ... | 02/24/2004 |
| 6682956 | Method of fabricating package having metal runner A method for fabricating a chip size package having a metal runner capable of preventing split generation due to stress in a solder mask made of a polymer such as BCB. The disclosed method includes steps of forming a stress buffer layer on a semiconductor... | 01/27/2004 |
| 6674158 | Semiconductor die package having a UV cured polymeric die coating A permanent protective semiconductor die coating made from a polymer that is fully curable through exposure to ultra violet light. A mixture of polymer resin and a photoactive compound is applied to the die and then cured through exposure to ultraviolet l... | 01/06/2004 |
| 6667235 | Semiconductor device and manufacturing method therefor An undercut portion is provided in the side surface of a wiring pattern formed over the electrode terminal forming surface of a semiconductor element so that when the top of the electrode terminal forming surface of the semiconductor element is sealed, a ... | 12/23/2003 |
| 6664171 | Method of alloying a semiconductor device A method for alloying a semiconductor substrate upon which wordlines enclosed in spacers have been formed, with the substrate exposed between the wordlines. A thin sealing layer is deposited over the substrate and the wordlines, the sealing layer helping ... | 12/16/2003 |
| 6657245 | Resin-encapsulated semiconductor apparatus and process for its fabrication The present invention provides a resin-encapsulated semiconductor apparatus comprising a semiconductor device having a ferroelectric film and a surface-protective film, and an encapsulant member comprising a resin; the surface-protective film being formed... | 12/02/2003 |
| 6657299 | Semiconductor with a stress reduction layer and manufacturing method therefor A surface of a metal wiring formed over a portion of a substrate is oxidized and annealed to generate a stress reduction layer. Then a passsivation layer is deposited over the stress reduction layer and the remaining portions of the substrate so that a se... | 12/02/2003 |
| 6646346 | Integrated circuit metallization using a titanium/aluminum alloy An integrated circuit metallization structure using a titanium/aluminum alloy, and a method to generate such a structure, provide reduced leakage current by allowing mobile impurities such as water, oxygen, and hydrogen to passivate structural defects in ... | 11/11/2003 |
| 6646347 | Semiconductor power device and method of formation In accordance with one embodiment, a stress buffer (40) is formed between a power metal structure (90) and passivation layer (30). The stress buffer (40) reduces the effects of stress imparted upon the passivation layer (30) by the power metal structure (... | 11/11/2003 |
| 6645855 | Method for fabricating an integrated semiconductor product A method fabricates an integrated semiconductor product. The first step is providing a semiconductor wafer that has preformed semiconductor components. The next step is forming at least one connection, in particular a polysilicon connection. The next step... | 11/11/2003 |
| 6642126 | Process for manufacturing a semiconductor wafer with passivation layer mask for etching with mechanical removal A process for manufacturing a semiconductor arrangement (3), whereby in particular a wafer (1) with a large number of semiconductor arrangements forming chips (7) is manufactured, and the wafer is divided afterward, and in this way the semiconductor arran... | 11/04/2003 |
| 6638631 | Thermal stable low elastic modulus material and device using the same The present invention provides a thermal stable low elastic modulus material, which has high thermal stability, is little in change in dynamic characteristics such as coefficient of thermal expansion and elastic modulus within a temperature of -50° C. to... | 10/28/2003 |
| 6638352 | Thermal stable low elastic modulus material and device using the same The present invention provides a thermal stable low elastic modulus material, which has high thermal stability, is little in change in dynamic characteristics such as coefficient of thermal expansion and elastic modulus within a temperature of -50° C. to... | 10/28/2003 |
| 6639285 | Method for fabricating a semiconductor device A method for making a semiconductor device is provided. The method allows for depositing a layer of a doped dielectric. The method further allows for executing plasma etching so that one or more etchant gases flow over the layer of doped dielectric. A red... | 10/28/2003 |
| 6638867 | Method for forming a top interconnection level and bonding pads on an integrated circuit chip A method for forming a top interconnection level and bonding pads for an integrated circuit chip is described. The interconnection level is formed by a damascene type process. Bonding pads are placed above the plane of the wiring channels of the interconn... | 10/28/2003 |
| 6630402 | Integrated circuit resistant to the formation of cracks in a passivation layer In integrated circuits produced by etching and damascene techniques, it is common for cracking to occur in dielectric material surrounding an interconnect metal layer integrated into the device, presumably as a result of the transfer of stresses from the ... | 10/07/2003 |
| 6617630 | Resin-encapsulated semiconductor apparatus and process for its fabrication The present invention provides a resin-encapsulated semiconductor apparatus comprising a semiconductor device having a ferroelectric film and a surface-protective film, and an encapsulant member comprising a resin; the surface-protective film being formed... | 09/09/2003 |
| 6617674 | Semiconductor package and method of preparing same A semiconductor package comprising a wafer having an active surface comprising at least one integrated circuit, wherein each integrated circuit has a plurality of bond pads; and a cured silicone layer covering the surface of the wafer, provided at least a... | 09/09/2003 |
| 6613696 | Method of forming composite silicon oxide layer over a semiconductor device A method of forming a composite silicon oxide layer over a semiconductor device. The composite silicon oxide layer is formed between the semiconductor device and a doped silicate glass layer. The composite silicon oxide layer comprises two silicon oxide l... | 09/02/2003 |
| 6605522 | Method of manufacturing a semiconductor device having a protruding bump electrode A present semiconductor device includes a plurality of bump electrodes formed over a semiconductor substrate to allow signals to be input and output to and from a semiconductor element. After the formation of the bump electrodes an organic insulting film ... | 08/12/2003 |
| 6599687 | Process for producing structured protective and insulating layers A process for producing structured or patterned protective and insulating layers includes applying a solution of a photosensitive polyhydroxyamide or polyhydroxyimide to a substrate and drying. The layer is patterned or structured by irradiation with UV l... | 07/29/2003 |
| 6600006 | Positive-type photosensitive polyimide precursor and composition comprising the same A polyamic ester prepared by partially substituting hydrogen atoms of carboxylic groups of a polyamic acid with acid labile groups, the polyamic ester comprising one or more repeating units represented by Formula 1, and each of at least one terminal of th... | 07/29/2003 |
| 6596633 | Method for manufacturing a semiconductor device The semiconductor device comprises a silicon substrate, a first metal pattern layer which is deposited on the silicon substrate, an inter metal dielectric which is deposited on the silicon substrate including the first metal pattern layer and on which a c... | 07/22/2003 |
| 6566737 | Passivation structure for an integrated circuit A novel passivation structure and its method of fabrication. According to the present invention a first dielectric layer is formed upon a conductive layer formed over a substrate. The first dielectric layer and the conductive layer are then patterned into... | 05/20/2003 |
| 6563196 | Semiconductor wafer, semiconductor device and manufacturing method therefor The invention aims to easily suppress chipping on the reverse face of a semiconductor when a semiconductor wafer is cut, and to make it possible to easily prevent edge contact of bonding wires. A resin film (14) is formed at the periphery of boundary regi... | 05/13/2003 |
| 6563219 | Passivation integrity improvements An exemplary implementation of the invention is a process for forming passivation protection on a semiconductor assembly by the steps of: forming a layer of oxide over patterned metal lines having sidewalls; forming a first passivation layer of silicon ni... | 05/13/2003 |
| 6559540 | Flip-chip semiconductor device and method of forming the same The present invention provides a semiconductor device comprising: a semiconductor substrate; at least a pad electrode provided over the semiconductor substrate; a passivation film provided over the semiconductor substrate; an insulative resin stress buffe... | 05/06/2003 |
| 6544908 | Ammonia gas passivation on nitride encapsulated devices A method for passivating at least interfaces between structures formed from a material including silicon and adjacent dielectric structures so as to reduce a concentration of dangling silicon bonds at these interfaces and to reduce or eliminate the occurr... | 04/08/2003 |
| 6541373 | Manufacture method for semiconductor with small variation in MOS threshold voltage After a MOS type transistor is formed on the surface of a semiconductor substrate, an interlayer insulating film covering the transistor is formed. The insulating film includes a silicon oxide film made of hydrogen silsesquioxane resin in a ceramic state.... | 04/01/2003 |
| 6531344 | High frequency gallium arsenide MMIC die coating method A moisture resistant conformal coating (14) effectively protects high frequency circuits such as gallium arsenide MMICs from humidity and environmental contamination without the performance degradation inherent in conventionally applied conformal coatings... | 03/11/2003 |
| 6528392 | Dicing configuration for separating a semiconductor component from a semiconductor wafer The dicing configuration for separating a semiconductor component from a semiconductor wafer is formed with a rupture joint which is created together with connecting holes that interconnect metallization planes, in a transition area between a scribe line ... | 03/04/2003 |
