Class 257/E23.123 - Characterized by arrangement or shape (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E23.116. This subclass
No. of patents: 34
Last issue date: 10/21/2008

Number	Title	Issue Date
7439598	Microelectronic imaging units Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method includes coupling a plurality of singulated imaging dies to a support member. The individua...	10/21/2008
7429794	Multi-chip packaged integrated circuit device for transmitting signals from one chip to another chip In a multi-chip packaged integrated circuit device for transmitting signals from one chip to another chip, in the case where not only a logic circuit of a first chip but also a logic circuit of a second chip requires an input signal, the multi-chip packaged integrat...	09/30/2008
7408264	SMT passive device noflow underfill methodology and structure An electronic fabrication process and structure is provided for attaching discrete passive surface mount devices (SMD) to a substrate in a single step. A liquid noflow resin encapsulant containing flux material is dispensed between presoldered pads on a substrate. T...	08/05/2008
7375419	Stacked mass storage flash memory package A stacked multiple offset chip device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and sub...	05/20/2008
7361984	Chip package structure A chip package structure including a lead frame, at least one first bonding wire, at least one second bonding wire, third bonding wires and an encapsulant is provided. The lead frame includes a die pad, inner leads and at least one bus bar, wherein the bus bar is di...	04/22/2008
7342296	Wafer street buffer layer The present invention provides a separating process of a semiconductor device package of wafer level package. The method comprises a step of etching a substrate to form recesses. Then a buffer layer is formed on the first surface of the substrate, wherein the buffer...	03/11/2008
7285867	Wiring structure on semiconductor substrate and method of fabricating the same A semiconductor device includes a semiconductor substrate having a plurality of connecting pads on one surface, an insulating film formed on one surface of the semiconductor substrate. The insulating film has holes each corresponding to one of the connecting pads, a...	10/23/2007
7262506	Stacked mass storage flash memory package A stacked multiple offset chip device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and sub...	08/28/2007
7205658	Singulation method used in leadless packaging process A singulation method used in leadless packaging process is disclosed. An array of molded products on an upper surface of a lead frame is utilized in the singulation method. The lead frame has a plurality of dambars between the molded products. The lower surface of t...	04/17/2007
7196410	Wafer packaging and singulation method A multi-device lid for a micro device wafer has a plurality of micro devices. The multi-device lid includes a multi-lid substrate configured to cover the plurality of micro devices of the micro device wafer. The multi-lid substrate has a trench pattern with intersec...	03/27/2007
7151014	Underfilling process in a molded matrix array package using flow front modifying solder resist Placing a flow modifier on a package substrate to create two flow fronts on a molded matrix array package. A flow modifier may be laid on a package substrate to a height that blocks off the bottom of other substrates (e.g., dice) coupled to the package substrate. By...	12/19/2006
7119449	Enhancement of underfill physical properties by the addition of thermotropic cellulose An electrical component having improved impact resistance and improved tolerance for thermal cycling, without sacrificing high-temperature performance, and without requiring unconventional and expensive manufacturing techniques includes an electric device mounted on...	10/10/2006
7109592	SMT passive device noflow underfill methodology and structure An electronic fabrication process and structure is provided for attaching discrete passive surface mount devices (SMD) to a substrate in a single step. A liquid noflow resin encapsulant containing flux material is dispensed between presoldered pads on a substrate. T...	09/19/2006
6620706	Condensed memory matrix A condensed memory matrix is fabricated by conductively connecting the attachment bumps of a substrate with the attachment bumps of a wafer of DRAM chips and physically bonding the juxtaposed surfaces of the substrate and the wafer with a dielectric curab...	09/16/2003
6593665	Protective envelope for a semiconductor integrated circuit A protective envelope, made of a plastics material for enclosing a semiconductor integrated circuit, includes a flattened parallelepiped body having a sidewall formed of first and second portions set to converge toward each other. The envelope also includ...	07/15/2003
6433417	Electronic component having improved soldering performance and adhesion properties of the lead wires Electrodes of the electronic component chip is electrically connected with the end parts of the leads and the electronic component chip and the end parts of the leads are covered by the package with the leads which are extended out from the package are be...	08/13/2002
6396159	Semiconductor device A semiconductor device which eliminates a thermal stress in the semiconductor device or warp in a package of the semiconductor device to increase reliability. To achieve this, the semiconductor device has a structure in which an insulation flexible film a...	05/28/2002
6365976	Integrated circuit device with depressions for receiving solder balls and method of fabrication A semiconductor device, especially a Ball Grid Array or Chip Scale Package, comprising an integrated circuit chip having at least one input/output terminal; a body of encapsulation material molded around said chip, forming a generally flat surface includi...	04/02/2002
6307262	Condensed memory matrix A condensed memory matrix is fabricated by conductively connecting the attachment bumps of a substrate with the attachment bumps of a wafer of DRAM chips and physically bonding the juxtaposed surfaces of the substrate and the wafer with a dielectric curab...	10/23/2001
6133630	Condensed memory matrix A condensed memory matrix is fabricated by conductively connecting the attachment bumps of a substrate with the attachment bumps of a wafer of DRAM chips and physically bonding the juxtaposed surfaces of the substrate and the wafer with a dielectric curab...	10/17/2000
6071757	Condensed memory matrix A condensed memory matrix is fabricated by conductively connecting the attachment bumps of a substrate with the attachment bumps of a wafer of DRAM chips and physically bonding the juxtaposed surfaces of the substrate and the wafer with a dielectric curab...	06/06/2000
5978227	Integrated circuit packages having an externally mounted lead frame having bifurcated distal lead ends The present invention is a rail-less bus system for a high density integrated circuit package, or module, made up of a plurality of vertically stacked high density integrated circuit devices. Each device has leads extending therefrom with bifurcated or tr...	11/02/1999
5977629	Condensed memory matrix A condensed memory matrix is fabricated by conductively connecting the attachment bumps of a substrate with the attachment bumps of a wafer of DRAM chips and physically bonding the juxtaposed surfaces of the substrate and the wafer with a dielectric curab...	11/02/1999
5945692	Semiconductor device and method of fabricating same There is disclosed a semiconductor device having an MOS gate for reducing variations in threshold voltage (Vth) with time wherein a surface protective film is not formed in a device area including channels but only in a device peripheral area, ...	08/31/1999
5905305	Condensed memory matrix A condensed memory matrix is fabricated by conductively connecting the attachment bumps of a substrate with the attachment bumps of a wafer of DRAM chips and physically bonding the juxtaposed surfaces of the substrate and the wafer with a dielectric curab...	05/18/1999
5864175	Wrap-resistant ultra-thin integrated circuit package fabrication method The present invention provides a method for fabricating modified integrated circuit packages that are ultra-thin and resist warping. The integrated circuit packages are made thinner by removing some of the casing material uniformly from the upper and lowe...	01/26/1999
5843807	Method of manufacturing an ultra-high density warp-resistant memory module An ultra high-density integrated circuit module which includes a plurality of individual high-density integrated circuit packages. A plurality of the ultra high-density integrated circuit memory modules may be combined to form an ultra high-density memory...	12/01/1998
5828125	Ultra-high density warp-resistant memory module An ultra high-density integrated circuit module which includes a plurality of individual high-density integrated circuit packages. A plurality of the ultra high-density integrated circuit memory modules may be combined to form an ultra high-density memory...	10/27/1998
5801437	Three-dimensional warp-resistant integrated circuit module method and apparatus A method and apparatus for achieving a three-dimensional high density warp-resistant integrated circuit module is provided. Selected individual integrated circuit packages which comprise the module are mounted with a thin stiffener, or a thin layer of mat...	09/01/1998
5644161	Ultra-high density warp-resistant memory module An ultra high-density integrated circuit module which includes a plurality of individual high-density integrated circuit packages. A plurality of the ultra high-density integrated circuit memory modules may be combined to form an ultra high-density memory...	07/01/1997
5600181	Hermetically sealed high density multi-chip package An on-board chip package has a hermetically sealed connector mechanically secured to a printed wiring board and electrically connected to input/output pads on the board. Chip dies are mechanically bonded to the board and then individually encapsulated wit...	02/04/1997
5581121	Warp-resistant ultra-thin integrated circuit package The present invention provides a method for fabricating modified integrated circuit packages that are ultra-thin and resist warping. The integrated circuit packages are made thinner by removing some of the casing material uniformly from the upper and lowe...	12/03/1996
5369058	Warp-resistent ultra-thin integrated circuit package fabrication method The present invention provides a method for fabricating modified integrated circuit packages that are ultra-thin and resist warping. The integrated circuit packages are made thinner by removing some of the casing material uniformly from the upper and lowe...	11/29/1994
5369056	Warp-resistent ultra-thin integrated circuit package fabrication method The present invention provides a method for fabricating modified integrated circuit packages that are ultra-thin and resist warping. The integrated circuit packages are made thinner by removing some of the casing material uniformly from the upper and lowe...	11/29/1994

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Class 257/E23.123 - Characterized by arrangement or shape (EPO)