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| Number | Title | Issue Date |
| 7443025 | Thermally improved placement of power-dissipating components onto a circuit board The invention refers to an electronic system, comprising several power-dissipating components, and a circuit board, wherein said power-dissipating components are mounted both to a top side and a bottom side of said circuit board. Further, the invention refers to met... | 10/28/2008 |
| 7429785 | Stacked integrated circuit chip assembly A stacked arrangement of integrated circuit chips are bonded to a lead frame. Two side-by-side integrated circuit chips have bottom contact pads bonded to a lead frame structure having contact terminals. The two side-by-side integrated circuits have top contact pads... | 09/30/2008 |
| 7425758 | Metal core foldover package structures Chip-scale packages and assemblies thereof and methods of fabricating such packages including Chip-On-Board, Board-On-Chip, and vertically stacked Package-On-Package modules are disclosed. The chip-scale package includes a core member of a metal or alloy having a re... | 09/16/2008 |
| 7408244 | Semiconductor package and stack arrangement thereof A semiconductor package includes a semiconductor chip electrically connected to a plurality of leads arranged at the periphery of the semiconductor chip wherein each of the leads is bent to have a first portion exposed from the upper surface of the semiconductor pac... | 08/05/2008 |
| 7402912 | Method and power control structure for managing plurality of voltage islands A power control method and power control structures are provided for managing a plurality of voltage islands of a functional chip. The power control structure includes a supply control and partition chip positioned between a substrate carrier and a functional chip i... | 07/22/2008 |
| 7391106 | Stack type package A stack type semiconductor package uses rigid, C-shaped guide substrates that hold semiconductor packages stacked in place and which also provide signal pathways between the stacked semiconductors and contact surfaces of the package. The C-shaped guide eliminate sho... | 06/24/2008 |
| 7385283 | Three dimensional integrated circuit and method of making the same A three dimensional integrated circuit structure includes at least first and second devices, each device comprising a substrate and a device layer formed over the substrate, the first and second devices being bonded together in a stack, wherein the bond between the ... | 06/10/2008 |
| 7378726 | Stacked packages with interconnecting pins A system may include a first integrated circuit package including a first integrated circuit die and a first integrated circuit package substrate defining a first plurality of openings, a second integrated circuit package including a second integrated circuit die an... | 05/27/2008 |
| 7375420 | Large area transducer array A large area transducer array comprising a substrate having a front side and a backside, a plurality of transducers disposed on the front side of the substrate and patterned in the form of a two-dimensional transducer array in the X-Y plane, a plurality of connector... | 05/20/2008 |
| 7375418 | Interposer stacking system and method The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices with connections between the feet of leads of an upper IC element and the upper shoulder of leads of a lower IC element while t... | 05/20/2008 |
| 7372140 | Memory module with different types of multi chip packages In an embodiment, a memory module includes a first group of multi chip packages, including one or more non-volatile memories, and a second group of multi chip packages, including one or more volatile memories, wherein the first and second groups of multi chip packag... | 05/13/2008 |
| 7368811 | Multi-chip package and method for manufacturing the same A multi-chip package and method for manufacturing are disclosed. The multi-chip package may include a substrate, a lower semiconductor chip mounted on the substrate, a first electrical connection for electrically connecting the substrate and the lower semiconductor ... | 05/06/2008 |
| 7355273 | Semiconductor dice having back side redistribution layer accessed using through-silicon vias, methods An apparatus and method of rerouting redistribution lines from an active surface of a semiconductor substrate to a back surface thereof and assembling and packaging individual and multiple semiconductor dice with such rerouted redistribution lines formed thereon. Th... | 04/08/2008 |
| 7338837 | Semiconductor packages for enhanced number of terminals, speed and power performance An integrated circuit device package with a first part (101) having a cavity (104) to mount the chip (105), further I/O terminals (102) on the top surface and terminals (103) on the bottom surface. The chip has contact pads (107... | 03/04/2008 |
| 7335974 | Multi stack packaging chip and method of manufacturing the same A multi stack packaging chip and a method of manufacturing the chip are provided. The method includes forming at least one second circuit element on a first wafer; forming a second wafer having a cavity and a one third circuit element formed opposite to the cavity; ... | 02/26/2008 |
| 7327021 | Multi-level semiconductor module A semiconductor module is formed by alternately stacking resin boards on which semiconductor chips are mounted and sheet members having openings larger than the semiconductor chips and bonded to the resin boards. One of the resin boards located at the bottom has a t... | 02/05/2008 |
| 7323789 | Multiple chip package and IC chips A clock output pad and a return clock receiving pad are disposed on a logic chip at a portion near a side of an integrated circuit chip and a portion near another side of the integrated circuit chip that opposes to the side. A clock receiving pad is disposed on a me... | 01/29/2008 |
| 7317247 | Semiconductor package having heat spreader and package stack using the same A semiconductor package which can be stacked to form a package stack that includes a semiconductor chip with bonding pads, a board having contact pads on its upper surface and bump pads on its lower surface, a heat spreader attached to the rear side of the semicondu... | 01/08/2008 |
| 7304375 | Castellation wafer level packaging of integrated circuit chips Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and i... | 12/04/2007 |
| 7301242 | Programmable system in package Some embodiments of the invention provide a programmable system in package (“PSiP”). The PSiP includes a single IC housing, a substrate and several IC's that are arranged within the single IC housing. At least one of the IC's is a configurable IC. In some embodi... | 11/27/2007 |
| 7301233 | Semiconductor chip package with thermoelectric cooler The semiconductor chip package may include a substrate having circuit patterns and substrate pads connected with the circuit patterns. At least one semiconductor chip is mounted on the substrate, and a thermoelectric cooler having a P-type material plate and an N-ty... | 11/27/2007 |
| 7298032 | Semiconductor multi-chip package and fabrication method A multi-chip package comprises a package substrate having bond fingers disposed thereon. A first chip have center bonding pads formed on a substantially center portion thereof. The first chip is disposed on the package substrate. Insulating support structures are fo... | 11/20/2007 |
| 7298038 | Integrated circuit package system including die stacking An integrated circuit package system including a leadframe having an aperture provided therein and an integrated circuit package mounted to the leadframe over or under the aperture. A die is mounted within the aperture to the integrated circuit package and the die i... | 11/20/2007 |
| 7298037 | Stacked integrated circuit package-in-package system with recessed spacer A stacked integrated circuit package-in-package system is provided forming a first integrated circuit spacer package including a mold compound with a recess provided therein, stacking the first integrated circuit spacer package on an integrated circuit die on a subs... | 11/20/2007 |
| 7288837 | Semiconductor device and its writing method A semiconductor device mounted on a mother board has a circuit board to be positioned on the mother board and a semiconductor chip positioned on the circuit board. The circuit board has a connection pad, a relay pad spaced away from the connection pad, and a wire co... | 10/30/2007 |
| 7288835 | Integrated circuit package-in-package system An integrated circuit package-in-package system is provided forming a first integrated circuit package having a first interface, stacking a second integrated circuit package having a second interface above the first integrated circuit package, fitting the first inte... | 10/30/2007 |
| 7282791 | Stacked semiconductor device and semiconductor memory module A semiconductor device module includes a wiring substrate, a plurality of stacked semiconductor devices and a damping impedance circuit. The plurality of stacked semiconductor devices are provided on the wiring substrate and connected with a signal in a stubless man... | 10/16/2007 |
| 7279785 | Stacked die package system A stacked die package system including forming a bottom package including a bottom substrate and a bottom die mounted and electrically connected under the bottom substrate and forming a top package including a top substrate and a top die mounted and electrically con... | 10/09/2007 |
| 7279784 | Semiconductor package A semiconductor package mainly includes a semiconductor chip and a plurality of L-shaped leads arranged at the periphery of the semiconductor chip. Each of the L-shaped leads has an inner lead portion exposed out of the lower surface of the semiconductor package and... | 10/09/2007 |
| 7276786 | Stacked board-on-chip package having mirroring structure and dual inline memory module on which the stacked board-on-chip packages are mounted Embodiments of the invention include a stacked board-on-chip (BOC) package having a mirroring structure and a dual inline memory module (DIMM) on which the stacked BOC package is mounted. A bottom surface of a first semiconductor chip faces a bottom surface of a sec... | 10/02/2007 |
| 7268019 | Method and apparatus for high temperature operation of electronics Embodiments of methods and apparatus for high temperature operation of electronics according to the invention are disclosed. One embodiment of the invention generally includes an integrated circuit package having a substrate. A plurality of integrated circuits are c... | 09/11/2007 |
| 7265442 | Stacked package integrated circuit The invention relates to an integrated circuit, electronic device, and method for assembling an integrated circuit package with at least one bottom module with a stacked die package comprising at least two dies within one single mold cap. To allow chip area reductio... | 09/04/2007 |
| 7265441 | Stackable single package and stacked multi-chip assembly A stackable packaged chip includes a substrate with a conductive wiring formed therein or thereon. The substrate further includes a plurality of substrate contact pads arranged around a periphery portion of the substrate. A chip mounted on the substrate including co... | 09/04/2007 |
| 7262080 | BGA package with stacked semiconductor chips and method of manufacturing the same A package with two or more stacked semiconductor chips and a method of manufacturing the same. In the method, an upper semiconductor chip package and a lower semiconductor chip package are prepared. Solder balls are formed on a substrate of the lower package to conn... | 08/28/2007 |
| 7262508 | Integrated circuit incorporating flip chip and wire bonding An integrated circuit incorporates flip chip and wire bonding techniques to provide an improved integrated circuit device. The integrated circuit device includes a package having a first plurality of bonding pads and a semiconductor substrate within the integrated c... | 08/28/2007 |
| 7253530 | Method for producing chip stacks A plurality of interconnect layers are produced on a top side of one or two semiconductor chips, and are mutually isolated from one another in each case by insulation layers that are patterned in such a way that an interconnect layer applied as bridge makes contact ... | 08/07/2007 |
| 7247933 | Thin multiple semiconductor die package A method and apparatus for forming a multiple semiconductor die assembly (200, 300, 400) having a thin profile are presented. The semiconductor die assembly (200, 300, 400) comprises a plurality of die packages (100), with each die package (1... | 07/24/2007 |
| 7235870 | Microelectronic multi-chip module A method of fabricating a microelectronic multi-chip module comprises: providing a cavity down ball grid array having a die and solder balls on a die side thereof; providing a package including at least one die thereon on a die side thereof; stacking the package ont... | 06/26/2007 |
| 7193307 | Multi-layer FET array and method of fabricating A power array includes a plurality of FET power assemblies and each FET power assembly has at least one field effect transistor mounted to a ciruit board. The circuit boards are arranged atop each other. A power supply pin extends through the circuit boards and is c... | 03/20/2007 |
| 7187068 | Methods and apparatuses for providing stacked-die devices Methods and apparatuses to provide a stacked-die device comprised of stacked sub-packages. For one embodiment of the invention, each sub-package has interconnections formed on the die-side of the substrate for interconnecting to another sub-package. The dies and ass... | 03/06/2007 |
