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| Number | Title | Issue Date |
| 7442653 | Inter-metal dielectric of semiconductor device and manufacturing method thereof including plasma treating a plasma enhanced fluorosilicate glass An exemplary manufacturing method of an inter-metal dielectric of a semiconductor device according to an embodiment of the present invention includes forming a first silicon-rich oxide (SRO) layer on a silicon substrate provided with or otherwise having a copper lin... | 10/28/2008 |
| 7416938 | Inkjet patterning for thin-film capacitor fabrication, thin-film capacitors fabricated thereby, and systems containing same An integrated thin-film capacitor includes a dielectric disposed between a first electrode and a second electrode. The thin-film capacitor includes a dielectric disposed upon the first electrode, and the dielectric exhibits a substantially uniform heat-altered morph... | 08/26/2008 |
| 7384880 | Method for making a semiconductor device having a high-k gate dielectric A method for making a semiconductor device is described. That method comprises converting a hydrophobic surface of a substrate into a hydrophilic surface, and forming a high-k gate dielectric layer on the hydrophilic surface. ... | 06/10/2008 |
| 7352065 | Semiconductor devices having amorphous silicon-carbon dielectric and conducting layers A method for fabricating a semiconductor device having a plurality of layers, depositing a first layer comprising a medium-k dielectric barrier layer on one of the plurality of layers, depositing a second layer comprising a low-k dielectric layer on the first layer,... | 04/01/2008 |
| 7352061 | Flexible core for enhancement of package interconnect reliability An IC package is disclosed that comprises a core region disposed between upper and lower build-up layer regions. In one embodiment, the core region comprises a low modulus material. In an alternative embodiment the core region comprises a medium modulus material. In... | 04/01/2008 |
| 7323424 | Semiconductor constructions comprising cerium oxide and titanium oxide The invention includes semiconductor constructions comprising dielectric materials which contain cerium oxide and titanium oxide. The dielectric materials can contain a homogeneous distribution of cerium oxide and titanium oxide, and/or can contain a laminate of cer... | 01/29/2008 |
| 7323423 | Forming high-k dielectric layers on smooth substrates A buffer layer and a high-k metal oxide dielectric may be formed over a smooth silicon substrate. The substrate smoothness may reduce column growth of the high-k metal oxide gate dielectric. The surface of the substrate may be saturated with hydroxyl terminations pr... | 01/29/2008 |
| 7287320 | Method for programming a routing layout design through one via layer A method for programming a routing layout design through one via layer includes forming a plurality of metal traces on a first routing layer and a second routing layer, and positioning a plurality of vias within a via layer disposed between the first and second rout... | 10/30/2007 |
| 7268035 | Methods of forming semiconductor constructions comprising cerium oxide and titanium oxide The invention includes semiconductor constructions comprising dielectric materials which contain cerium oxide and titanium oxide. The dielectric materials can contain a homogeneous distribution of cerium oxide and titanium oxide, and/or can contain a laminate of cer... | 09/11/2007 |
| 7256139 | Methods and apparatus for e-beam treatment used to fabricate integrated circuit devices One embodiment of the present invention is a method for fabricating a low-k dielectric film that included steps of: (a) chemical vapor depositing a lower-k dielectric film; and (b) e-beam treating the lower-k dielectric film. ... | 08/14/2007 |
| 7240429 | Manufacturing method for a printed circuit board A conductor pattern is formed on a resin film which is made of a thermoplastic resin. Each single-sided conductor pattern film has via-holes filled with an electrically conductive paste. A printed conductor pattern and a printed resistor are formed on a ceramic subs... | 07/10/2007 |
| 7230332 | Chip package with embedded component A chip package is provided. The chip package includes at least one chip, an interconnection structure, a plurality of second pads and at least one panel-shaped component, wherein the chip includes a plurality of first pads on a surface thereof. The interconnection s... | 06/12/2007 |
| 7227240 | Semiconductor device with wire bond inductor and method A semiconductor device (10) includes a semiconductor die (20) and an inductor (30, 50) formed with a bonding wire (80) attached to a top surface (21) of the semiconductor die. The bonding wire is extended laterally a distance (L... | 06/05/2007 |
| 7164191 | Low relative permittivity SiOfilm including a porous material for use with a semiconductor device A low relative permittivity SiOx film excellent in heat resistance without using an alkali metal, fluorine, etc., a method for modifying an SiOx film to accomplish a further reduction of the relative permittivity of the low relative permittivit... | 01/16/2007 |
| 6686664 | Structure to accommodate increase in volume expansion during solder reflow Solder balls, such as, low melt C4 solder balls undergo volume expansion during reflow. Where the solder balls are encapsulated, expansion pressure can cause damage to device integrity. A volume expansion region in the semiconductor chip substrate beneath... | 02/03/2004 |
| 6680123 | Embedding resin An embedding resin embeds an electronic part in an object and has a dielectric constant of about 5 or less and tan δ of about 0.08 or less.... | 01/20/2004 |
| 6674155 | Chip carrier film, method of manufacturing the chip carrier film and liquid crystal display using the chip carrier film A chip carrier film comprising a metal wiring formed on a surface of a base film, a first insulating film covering the metal wiring excluding a semiconductor chip connecting pad portion and a terminal connecting pad portion, a semiconductor chip connected... | 01/06/2004 |
| 6670696 | Tape-carrier-package semiconductor device and a liquid crystal panel display using such a device as well as a method for testing the disconnection thereof A slit is formed in a polyimide substrate and a copper wiring pattern is formed on the surface of the polyimide substrate. Moreover, solder resist, which has a young's modulus in the range of 5 kgf/mm2 to 70 kgf/mm2 and contains a fi... | 12/30/2003 |
| 6670285 | Nitrogen-containing polymers as porogens in the preparation of highly porous, low dielectric constant materials Dielectric compositions comprised of porous polymeric matrices are prepared using nitrogen-containing polymers as pore-generating agents. The compositions are useful in the manufacture of electronic devices such as integrated circuit devices and integrate... | 12/30/2003 |
| 6667094 | Paste for screenprinting electric structures onto carrier substrates A paste for screen printing of electrical structures on substrates, in particular ceramic substrates, which includes a mixture of inorganic solid particles having high sintering temperature and an inorganic binding agent having a low sintering temperature... | 12/23/2003 |
| 6664127 | Method of manufacturing multi-layer printed wiring board In a method of manufacturing multi-layer printed wiring board, an uncured resin sheet is laminated on both surfaces of a printed wiring board having one or more layers, an organic cover film having a release property is laminated on the surfaces of the un... | 12/16/2003 |
| 6663946 | Multi-layer wiring substrate An object of the invention is to satisfy all of a high-density wiring package, soldering thermal resistance, an insulating property and high-frequency transmission characteristics. The invention is a multi-layer wiring substrate having a lamination of a p... | 12/16/2003 |
| 6660670 | Ceramics and method of preparing the same Ceramics containing a diopside crystal phase and a cordierite phase, the remainder being a glass phase and/or other ceramic crystal phases, and having an open porosity of not larger than 1%. The ceramics is obtained by firing at from 800 to 1050° C., and... | 12/09/2003 |
| 6660942 | Semiconductor device with an exposed external-connection terminal A wiring substrate equipped with a rerouted wiring having one end connected to an electronic-part mounting pad for electrically connecting an electronic part and another end connected to an external-connection terminal. In the wiring substrate, a low-elas... | 12/09/2003 |
| 6646063 | Semiconductor device and process for producing the same, and tablet comprising epoxy resin composition A tablet for producing a semiconductor device with substantially no bowing, comprising an epoxy resin composition comprising an epoxy resin and a curing agent, wherein the tablet has the characteristic of an amount reduced by heating being less than 0.05%... | 11/11/2003 |
| 6645631 | Flame retardant phosphorus element-containing epoxy resin compositions A flame retardant phosphorus element-containing epoxy resin composition substantially free of halogen, including: (I) a non-halogenated epoxy resin material selected from: (A) a non-halogenated phosphorus element-containing epoxy resin; (B) a mixture of... | 11/11/2003 |
| 6638352 | Thermal stable low elastic modulus material and device using the same The present invention provides a thermal stable low elastic modulus material, which has high thermal stability, is little in change in dynamic characteristics such as coefficient of thermal expansion and elastic modulus within a temperature of -50° C. to... | 10/28/2003 |
| 6638631 | Thermal stable low elastic modulus material and device using the same The present invention provides a thermal stable low elastic modulus material, which has high thermal stability, is little in change in dynamic characteristics such as coefficient of thermal expansion and elastic modulus within a temperature of -50° C. to... | 10/28/2003 |
| 6635510 | Method of making a parylene coating for soldermask A method for making an HDI circuit including backside connections uses parylene as a protective coating. The method includes the steps of: procuring an insulating substrate including an active chip which has exposed electrical or thermal connection(s) on ... | 10/21/2003 |
| 6632996 | Micro-ball grid array package tape including tap for testing A package tape for testing a chip assembled by a packaging method such as a micro-ball grid array (BGA) package, whereby the chip is designed to face downward. The package tape includes one or more taps, disposed on a guard area other than an area where a... | 10/14/2003 |
| 6621166 | Five layer adhesive/insulator/metal/insulator/adhesive tape for semiconductor die packaging A novel five-layer tape is provided for applications such as bonding, interconnection and insulation of different parts of a semiconductor package at the same time. The five layer tape includes a metal conductive layer that is sandwiched between two insul... | 09/16/2003 |
| 6616984 | Forming viaholes in composition of cyanate, bismaleimide, epoxy resin and unsaturated aromatic glycidyl A process of forming vias in a composition comprising (a) applying a layer of a composition containing (i) a cyanate ester, (ii) a bismaleimide, (iii) a co-curing agent having the structure R1 --Ar--R2 wherein Ar is at least one aryl ... | 09/09/2003 |
| 6602616 | Composite multilayer ceramic electronic parts and method of manufacturing the same A composite multilayer ceramic electronic part includes a high dielectric-constant layer and at least one low dielectric-constant layer laminated with each other, the high dielectric-constant layer including a high dielectric-constant material and has a r... | 08/05/2003 |
| 6599637 | Silicon nitride composite substrate A Si3 N4 composite substrate which manifests no generation of cracking on the substrate even by mechanical shock or thermal shock, and is excellent in heat radiation property and heat-cycle-resistance property is obtained by using a ... | 07/29/2003 |
| 6597058 | Method of forming defect-free ceramic structures using thermally depolymerizable surface layer This invention relates generally to a new method of forming semiconductor substrates with defect-free surface metallurgical features. In particular, the invention related to a method for providing surface protected ceramic green sheet laminates using at l... | 07/22/2003 |
| 6596382 | Multilayered board and method for fabricating the same A multilayered board includes a laminate including a plurality of glass-containing insulating layers, each glass-containing insulating layer being provided with an electrode on the surface thereof. The glass-containing insulating layer is formed by firing... | 07/22/2003 |
| 6586513 | Aqueous dispersion for electrodeposition, high dielectric constant film and electronic parts It is an object of the invention to provide an aqueous dispersion for electrodeposition which has excellent shelf life and can form thin, high dielectric constant films, as well as a high dielectric constant film formed from the aqueous dispersion and ele... | 07/01/2003 |
| 6582541 | Monolithic ceramic substrate, manufacturing and designing methods therefor, and electronic device In a green laminate body including a plurality of base green layers and a plurality of constraining green layers for forming a monolithic ceramic substrate by using a non-shrinking process, when the thicknesses of the base green layers differ from each ot... | 06/24/2003 |
| 6580143 | Thin-film circuit substrate and method of producing same A surface modification layer having a surface modification coefficient of 0.1 to 0.5 is formed on the surface of an organic insulating film on a substrate. A metal wiring is provided on the surface of the organic insulating film having the surface modific... | 06/17/2003 |
| 6569711 | Methods and apparatus for balancing differences in thermal expansion in electronic packaging CTE differentials between chips and organic dielectric carriers, boards or other substrates to which the chips are attached are accommodated with a layer of a thermoplastic material, preferably a thermotropic polymer whose physical properties can be alter... | 05/27/2003 |
