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| Number | Title | Issue Date |
| 7443030 | Thin silicon based substrate Embodiments of the invention provide a device with a die and a substrate having a similar coefficient of thermal expansion to that of the die. The substrate may comprise a silicon base layer. Build up layers may be formed on the side of the base layer further from t... | 10/28/2008 |
| 7436056 | Electronic component package An electronic component package includes a dielectric substrate having a first surface where an electronic component is sealed. A first signal line connecting to the electronic component and a first ground conductor are formed on the first surface of the dielectric ... | 10/14/2008 |
| 7427562 | Method for fabricating closed vias in a printed circuit board A method for forming closed vias in a multilayer printed circuit board. A dielectric layer is laminated to one side of a central core having a metal layer on each side. A second dielectric layer is laminated to the other side of the central core. Closed vias in the ... | 09/23/2008 |
| 7420272 | Two-sided wafer escape package A method of forming an electronic component package includes: forming electrically conductive traces for connecting first selected bond pads of a plurality of bond pads on a first surface of an electronic component to corresponding bonding locations formed on a seco... | 09/02/2008 |
| 7411306 | Packaging structure and method of an image sensor module This invention relates to a packaging structure and method of an image sensor module. The method comprises: providing a transparent substrate having a first patterned conductive layer; carrying an image sensor integrated circuit chip having a photosensitive active a... | 08/12/2008 |
| 7405473 | Techniques for optimizing electrical performance and layout efficiency in connectors with via placement and routing Techniques are provided for placing and routing vias that conduct signals through a connector between two electrical units. Vias that conduct a first set of signals are placed next to vias that provide return paths for the first set of signals to reduce cross-talk o... | 07/29/2008 |
| 7405485 | Semiconductor device A semiconductor device provided with a first semiconductor chip having a first functional surface formed with a first functional element and a first rear surface, a second semiconductor chip having a second functional surface which is formed with a second functional... | 07/29/2008 |
| 7388293 | Interposer method of fabricating same, and semiconductor device using the same having two portions with different constructions An interposer to be interposed between a semiconductor chip to be mounted thereon and a packaging board has an interposer portion made of a semiconductor material and an interposer portion provided around the foregoing interposer portion integrally therewith. On bot... | 06/17/2008 |
| 7368812 | Interposers for chip-scale packages and intermediates thereof A carrier substrate, or interposer, for use in a chip-scale package includes a material, such as a semiconductive material, that has a coefficient of thermal expansion that is the same or similar to that of the semiconductor device to be secured thereto. The interpo... | 05/06/2008 |
| 7365436 | Substrate having a penetrating via and wiring connected to the penetrating via and a method for manufacturing the same A disclosed substrate includes a base member having a through-hole, and a conductive metal filling in the through-hole so as to form a penetrating via. The penetrating via contains a conductive core member that is substantially at the central axis of the through-hol... | 04/29/2008 |
| 7339260 | Wiring board providing impedance matching A wiring board comprising: a plate core having a first main surface and a second main surface; conductor layers including a conductor line; dielectric layers laminated alternately with said conductor layers on at least one of said first and second main surfaces; via... | 03/04/2008 |
| 7332799 | Packaged chip having features for improved signal transmission on the package A packaged chip is provided which includes a package element on which a signal-bearing conductive trace has an edge laterally adjacent to an edge of a reference conductive trace (e.g., ground trace) on the same face of a dielectric element, the two traces together f... | 02/19/2008 |
| 7307354 | Integrated circuit (IC) carrier assembly incorporating an integrated circuit (IC) retainer An integrated circuit (IC) carrier assembly includes a printed circuit board (PCB). A carrier is soldered to the PCB. The carrier includes a grid of electrical contact islands surrounding a receiving zone for receiving an IC. Pairs of adjacent islands are interconne... | 12/11/2007 |
| 7298035 | Semiconductor device and a method of assembling a semiconductor device A semiconductor device includes a substrate having first and second surfaces, the substrate having an opening; a first adhesive layer provided on the first surface; a second adhesive layer provided under the second surface; a third adhesive layer provided around the... | 11/20/2007 |
| 7279776 | Method of manufacturing semiconductor device and semiconductor device A silicon substrate has a protective film formed on each side. A semiconductor surface opening not smaller than a given region is formed by removing the protective film. A through-hole having an inner size smaller than the given region is formed in the opening by la... | 10/09/2007 |
| 7275316 | Method of embedding passive component within via A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein. ... | 10/02/2007 |
| 7276787 | Silicon chip carrier with conductive through-vias and method for fabricating same A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic... | 10/02/2007 |
| 7274105 | Thermal conductive electronics substrate and assembly An electronics assembly is provided including a circuit board substrate having a top surface and a bottom surface and a plurality of thermal conductive vias extending from the top surface to the bottom surface. At least one electronics package is mounted to the top ... | 09/25/2007 |
| 7262491 | Die pad for semiconductor packages and methods of making and using same A semiconductor device package comprising a semiconductor device and an electrically conductive lead frame at least partially covered by a molding compound. The electrically conductive lead frame includes a plurality of leads disposed proximate a perimeter of the pa... | 08/28/2007 |
| 7256496 | Semiconductor device having adhesion increasing film to prevent peeling A semiconductor device includes at least one semiconductor constructing body provided on one side of a base member, and having a semiconductor substrate and a plurality of external connecting electrodes provided on the semiconductor substrate. An insulating layer is... | 08/14/2007 |
| 7253505 | IC substrate with over voltage protection function The present invention relates to an IC substrate provided with over voltage protection functions and thus, a plurality of over voltage protection devices are provided on a single substrate to protect an IC chip directly. According to the present invention, there is ... | 08/07/2007 |
| 7253504 | Integrated circuit package and method An integrated circuit package includes a substrate having a central axis dividing the substrate into an upper half and a lower half and an integrated circuit coupled to the substrate. A layer is provided within the substrate in the lower half thereof that is configu... | 08/07/2007 |
| 7253514 | Self-supporting connecting element for a semiconductor chip A connecting element for electrically connecting a semiconductor chip and a superordinate circuit board includes an elastic metal strip that is bent forming two metal limbs with flattened limb ends, thus forming a base between the metal limbs which is suitable for c... | 08/07/2007 |
| 7247932 | Chip package with capacitor A chip package for semiconductor chips is provided by the method of forming a chip package includes the steps of forming a printed circuit board with a window therethrough; forming semiconductor chip connections of one or more primary chips which overlie the window ... | 07/24/2007 |
| 7247516 | Method for fabricating a leadless chip carrier Structure and method for fabrication of a leadless chip carrier have been disclosed. A disclosed embodiment comprises a substrate having a top surface for receiving a semiconductor die. The disclosed embodiment also comprises a printed circuit board attached to a bo... | 07/24/2007 |
| 7247937 | Mounting pad structure for wire-bonding type lead frame packages A chip package having a lead frame, a chip, a plurality of bonding wires, and an insulation material is provided. The lead frame comprises a die pad, a plurality of leads, a plurality of signal pads and a plurality of non-signal pads. The signal pads and non-signal ... | 07/24/2007 |
| 7244633 | Chip carrier substrate with a land grid array and external bond terminals A carrier for a semiconductor die has a substrate with a cavity formed in the substrate. The cavity has a bottom and sidewalls, and the sidewalls have a stepped tier. Electrically conductive contacts are disposed on an underside of the substrate. Electrically conduc... | 07/17/2007 |
| 7245022 | Semiconductor module with improved interposer structure and method for forming the same Under the present invention, a semiconductor chip is electrically connected to a substrate (e.g., organic, ceramic, etc.) by an interposer structure. The interposer structure comprises an elastomeric, compliant material that includes metallurgic through connections ... | 07/17/2007 |
| 7238967 | Light emitting diode A light emitting diode comprising: a base substrate having a pair of electrodes; a reflection cup installed on the base substrate; a light emitting element arranged at a bottom of the reflection cup; and a resin sealant enclosing the light emitting element; wherein ... | 07/03/2007 |
| 7230332 | Chip package with embedded component A chip package is provided. The chip package includes at least one chip, an interconnection structure, a plurality of second pads and at least one panel-shaped component, wherein the chip includes a plurality of first pads on a surface thereof. The interconnection s... | 06/12/2007 |
| 7217996 | Ball grid array socket having improved housing A ball grid array (BGA) socket includes an insulative housing (11), a number of terminals (12) and a protecting device (114). The insulative housing includes a mating surface (111), a mounting surface (112) opposite to mating surfa... | 05/15/2007 |
| 7205668 | Multi-layer printed circuit board wiring layout A multi-layer printed circuit board (PCB) includes a first wire layer, a middle layer above the first wire layer, a second wire layer above the middle layer, and a slanting via formed in the middle layer and the second wire layer. The manufacturing method includes t... | 04/17/2007 |
| 7196426 | Multilayered substrate for semiconductor device A multilayered substrate for a semiconductor device, which has a multilayered substrate body formed of a plurality sets of a conductor layer and an insulation layer, and having a face for mounting a semiconductor element thereon and another face for external connect... | 03/27/2007 |
| 7196427 | Structure having an integrated circuit on another integrated circuit with an intervening bent adhesive element Two or more semiconductor packages are stacked with an intervening element that is positioned between within an area surrounded by conductive bumps of a bottom surface of the overlying package. Different shapes of the intervening element are used depending upon how ... | 03/27/2007 |
| 7180170 | Lead-free integrated circuit package structure An integrated circuit package (60) has a substrate (12) with a first surface (51) for mounting a semiconductor die (20) and a second surface (52) defining a via (70). A lead (26) is formed by plating a conductive mate... | 02/20/2007 |
| 7170183 | Wafer level stacked package Disclosed are a wafer level stacked package and its manufacturing method. As one example, in such a wafer level stacked package, a first semiconductor die is electrically connected to an upper surface of a substrate and a second semiconductor die is electrically con... | 01/30/2007 |
| 7157372 | Coaxial through chip connection A method performed on a wafer having multiple chips, each including a doped semiconductor and substrate, involves etching an annulus trench partially into the substrate, metalizing the annulus trench with a metal, etching a via trench within the periphery of the ann... | 01/02/2007 |
| 7145251 | Colored conductive wires for a semiconductor package The surface of a solder ball and a conductive wire for a semiconductor package are coated with a predetermined colorant. Various colorants may be used according to the diameter and metal composition of the solder ball and the conductive wire. The colorant is formed ... | 12/05/2006 |
| 7141872 | Semiconductor device and method of manufacturing semiconductor device Disclosed is a method of manufacturing a semiconductor device, comprising preparing a first substrate including an integrated circuit chip, first connection terminals electrically connected to terminals of the integrated circuit chip, and a first connection portion ... | 11/28/2006 |
| 7119444 | Versatile system for charge dissipation in the formation of semiconductor device structures The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (200), obviating overstress or break down damage to a focal device structure (208) that might resul... | 10/10/2006 |
