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| Number | Title | Issue Date |
| 7429797 | Electronic device and carrier substrate Consistent with an example embodiment, an electronic device comprises a semiconductor device, particularly an integrated circuit, and a carrier substrate with conductive layers on the first side and the second side, and voltage supply and ground connections mutually... | 09/30/2008 |
| 7405479 | Wired circuit board A wired circuit board having terminals that can ensure large electrical connection areas while preventing shorting of adjacent terminals, to ensure that the terminals are electrically connected with external terminals through molten metal. An insulating base layer | 07/29/2008 |
| 7378721 | Chip on lead frame for small package speed sensor A sensor package apparatus includes a lead frame substrate that supports one or more electrical components, which are connected to and located on the lead frame substrate. A plurality of wire bonds are also provided, which electrically connect the electrical compone... | 05/27/2008 |
| 7372169 | Arrangement of conductive pads on grid array package and on circuit board The present invention discloses a dense arrangement in the conductors of a package and the corresponding conductive pads of a circuit board. The conductors and the corresponding conductive pads are separated into at least a first group in a peripheral region of the ... | 05/13/2008 |
| 7327039 | Nanoparticle filled underfill The invention provides electronic articles and methods of making said articles. The electronic articles comprise an electronic component bonded and electrically connected to a substrate using an underfill adhesive comprising the reaction product of a thermosetting r... | 02/05/2008 |
| 7327030 | Apparatus and method incorporating discrete passive components in an electronic package An apparatus and method for incorporating discrete passive components into an integrated circuit package. A metal layer is formed over a surface of a substrate. A layer of photosensitive material is then formed over the metal layer. Using standard photolithographic ... | 02/05/2008 |
| 7323774 | Integrated circuit package system with pedestal structure An integrated circuit package system includes providing a substrate having a bond finger thereon and forming a pedestal on a portion of the bond finger. A first die is mounted on the substrate and adjacent to the bond finger. A portion of the first die, a portion of... | 01/29/2008 |
| 7315072 | Semiconductor device capable of suppressing current concentration in pad and its manufacture method An interlayer insulating film is formed on a semiconductor substrate. An intra-layer insulating film is formed on the interlayer film. A recess is formed through the intra-layer film. The recess has a pad-part and a wiring-part continuous with the pad-part. The pad-... | 01/01/2008 |
| 7307354 | Integrated circuit (IC) carrier assembly incorporating an integrated circuit (IC) retainer An integrated circuit (IC) carrier assembly includes a printed circuit board (PCB). A carrier is soldered to the PCB. The carrier includes a grid of electrical contact islands surrounding a receiving zone for receiving an IC. Pairs of adjacent islands are interconne... | 12/11/2007 |
| 7282795 | Modifying a semiconductor device to provide electrical parameter monitoring A method of modifying a semiconductor device to provide electrical parameter monitoring. The device includes a semiconductor die and a package substrate. The substrate includes a conductive plane. The die is connected to the plane via a plurality of connection struc... | 10/16/2007 |
| 7253516 | Electronic device and carrier substrate for same Consistent with an example embodiment, an electronic device comprises an integrated circuit and a carrier substrate with a bottom and top conductive layer, and is provided with voltage supply, ground and signal transmission connections. In order to enable the use of... | 08/07/2007 |
| 7224066 | Bonding material and circuit device using the same A circuit device is provided in which the bonding reliability of a brazing material such as soft solder is improved. A circuit device of the present invention includes conductive patterns, a bonding material which fixes circuit elements to the conductive patterns, a... | 05/29/2007 |
| 7211904 | Pad structure for bonding pad and probe pad and manufacturing method thereof A mark-shaped pad. A bonding pad structure with at least one mark-shaped bonding pad comprises: a bottom metal layer disposed over the surface of a rectangular semiconductor substrate to connect the circuit electrically, an inter-metal dielectric layer disposed over... | 05/01/2007 |
| 7205658 | Singulation method used in leadless packaging process A singulation method used in leadless packaging process is disclosed. An array of molded products on an upper surface of a lead frame is utilized in the singulation method. The lead frame has a plurality of dambars between the molded products. The lower surface of t... | 04/17/2007 |
| 7202541 | Apparatus and method for transverse characterization of materials An apparatus for transverse characterization of materials includes a lower pattern of contacts, separated by spacings, a material, and an upper pattern of a multiplicity of contacts, separated by spacings differing from the spacings of the lower pattern. The transve... | 04/10/2007 |
| 7186592 | High performance, integrated, MOS-type semiconductor device and related manufacturing process An LDMOS device includes elementary MOS cells. The gate structure of the elementary cell includes a first conductor material finger. The LDMOS device includes first metal stripes for contacting source regions, second metal stripes for contacting drain regions, and t... | 03/06/2007 |
| 7173336 | Hybrid integrated circuit device A semiconductor device is provided wherein conductive paths 40, formed of crystal that grows better along the X-Y axis than along the Z axis, are embedded in an insulating resin 44, and the back surface of the conductive path 40 is exposed throu... | 02/06/2007 |
| 7166898 | Flip chip FET device In accordance with one embodiment of the invention, a semiconductor device includes conductive pad areas, and each conductive pad area is electrically connected to a plurality of metal traces which are in turn each connected to diffusions. A conductive contact eleme... | 01/23/2007 |
| 7164208 | Semiconductor device and method for manufacturing the same There is provided a semiconductor device in which the junction strength of land portions and external terminals is increased, the disconnection of the external terminal is surely prevented, and the connection reliability is ensured over an extended period of time. A... | 01/16/2007 |
| 7161251 | Partially populated ball grid design to accommodate landing pads close to the die Methods and structures to reduce in semiconductor packages the length of critical electrical connections between bond pads on one or multiple semiconductor chips and wire landing pads on a substrate have been achieved. An electrical connection becomes critical if hi... | 01/09/2007 |
| 7161250 | Projected contact structures for engaging bumped semiconductor devices and methods of making the same A bumped semiconductor device contact structure is disclosed including at least one non-planar contact pad having a plurality of projections extending therefrom for contacting at least one solder ball of a bumped integrated circuit (IC) device, such as a bumped die ... | 01/09/2007 |
| 6674108 | Gate length control for semiconductor chip design A semiconductor device includes first and second polysilicon areas on a chip. The first polysilicon area corresponds to circuit elements of the semiconductor device. At least some of the first polysilicon corresponds to polysilicon gates. At least some of... | 01/06/2004 |
| 6664624 | Semiconductor device and manufacturing method thereof A source electrode, a gate electrode, and a drain electrode formed on a front face active region of a semiconductor substrate in a shape of teeth of a comb are covered with an insulating film such as polyimede etc., as well as all of the upper surface and... | 12/16/2003 |
| 6649961 | Supporting gate contacts over source region on MOSFET devices Increasing the number of MOSFET gate bump contacts makes MOSFET gate contacts more durable and reliable. Extension of the under-bump metal laterally from the gate contact with the gate pad metallization out to two or more gate pads overlying the source pa... | 11/18/2003 |
| 6624484 | IGFET and tuning circuit A tuning circuit comprising a first reactance, a second reactance and a insulated gate field effect transistor having a gate arranged to receive a control signal. The first reactance is connected between the source of the field effect transistor and a fir... | 09/23/2003 |
| 6576936 | Bipolar transistor with an insulated gate electrode An IGBT is specified which can be produced in a simple manner yet can be turned on homogeneously. For this purpose, gate fingers are dispensed with and the gate current in the IGBT-Chip is forwarded, proceeding from the gate terminal, directly via the pol... | 06/10/2003 |
| 6566185 | Method of manufacturing a plural unit high frequency transistor A semiconductor device has a plurality of transistor units each of which is constituted by a unit prepared by arranging a plurality of unit cells each made up of a drain, gate, and source adjacent to each other on the major surface of a semiconductor subs... | 05/20/2003 |
| 6501159 | Power transistor module, power amplifier and method in the fabrication thereof The present invention relates to a power transistor module for radio frequency applications, particularly for use in an amplifier stage in a radio base station or in a ground transmitter for TV or radio, wherein said power transistor module comprises a su... | 12/31/2002 |
| 6486528 | Silicon segment programming apparatus and three terminal fuse configuration The present invention is a method and apparatus for programming a stack of segments wherein each segment includes a plurality of die which are interconnected through metal interconnects patterned on the surface of each segment. Once the segments are arran... | 11/26/2002 |
| 6476495 | Transistor which can minimize the DC resistance of the wiring and lead formed on a semiconductor chip A semiconductor chip 10 is provided to form a large number of cells constituting transistor units arranged on a planar and rectangular semiconductor substrate. On the front surface of the semiconductor chip 10, an emitter electrode 1 to be connected to an... | 11/05/2002 |
| 6445056 | Semiconductor capacitor device A semiconductor device comprising: a first interconnect layer 1 comprising a first electrode 10 and a second electrode 20 with a plurality of a tooth-shaped teeth 11, 21 and a connection portion 12, 22 for connecting the plurality of teeth, the first elec... | 09/03/2002 |
| 6424006 | Semiconductor component A semiconductor component, such as a high-frequency integrated circuit, includes a semiconductor substrate with one or more transistors formed thereon. First, second and third electrode terminals are respectively associated with the gate or base terminal,... | 07/23/2002 |
| 6372586 | Method for LDMOS transistor with thick copper interconnect A thick copper interconnection structure and method for an LDMOS transistor for power semiconductor devices. A large LDMOS transistor is formed of a plurality of source and drain diffusion regions to be coupled together to form the source and drain. Gate ... | 04/16/2002 |
| 6373082 | Compound semiconductor field effect transistor A compound semiconductor field effect transistor having, between a gate electrode and a drain electrode, a non-gate region which is the channel region not covered by the gate electrode, wherein a plurality of isolation regions are formed in the non-gate r... | 04/16/2002 |
| 6355972 | Semiconductor device and method of manufacturing same The invention relates to a semiconductor device comprising a bipolar transistor having a collector (1), a base (2) and an emitter (3) at its active area (A). The semiconductor body (10) of the device is covered with an insulating layer (20). At least a pa... | 03/12/2002 |
| 6346728 | Plural transistor device with multi-finger structure A semiconductor device has a plurality of transistor units each of which is constituted by a unit prepared by arranging a plurality of unit cells each made up of a drain, gate, and source adjacent to each other on the major surface of a semiconductor subs... | 02/12/2002 |
| 6323526 | Semiconductor integrated circuit A semiconductor integrated circuit includes four electrodes arranged in a matrix and a wire connecting between two electrodes which are diagonally positioned to each other and selected from the four electrodes. The two remaining electrodes are diagonally ... | 11/27/2001 |
| 6313512 | Low source inductance compact FET topology for power amplifiers A field effect transistor (FET) comprising a plurality of drain finger electrodes, source finger electrodes and gate finger electrodes disposed in an active region of a semiconductor substrate; a drain bus disposed outside the active region and electrical... | 11/06/2001 |
| 6274451 | Method of fabricating a gate-control electrode for an IGBT transistor This method of fabricating a gate-control electrode (28) for an insulated-gate bipolar transistor, from a plate of electrically conducting material which is covered with an electrically insulating layer (22) and, on one of its large faces, delimits a conn... | 08/14/2001 |
| 6255726 | Vertical interconnect process for silicon segments with dielectric isolation An apparatus for vertically interconnecting stacks of silicon segments. Each segment includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of metal inter... | 07/03/2001 |
