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Pneumatic Shoe Lacing Apparatus
This invention provides a pneumatic shoe lacing apparatus for the pneumatic lacing of shoe.
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| Number | Title | Issue Date |
| 7391107 | Signal routing on redistribution layer A semiconductor wafer has a dielectric layer, a metal last layer, a passivation layer, and a redistribution layer. The metal last layer is formed over the dielectric layer, and the metal last layer has first and second locations that are spaced apart from each other... | 06/24/2008 |
| 7262440 | Light emitting diode package and fabrication method thereof The present invention provides a light emitting diode (LED) package and the fabrication method thereof. The LED package includes a lower metal layer, and a first silicon layer, a first insulation layer, a second silicon layer, a second insulation layer, and a packag... | 08/28/2007 |
| 7247951 | Chip carrier with oxidation protection layer A chip carrier comprising a laminated layer and an oxidation protection layer is provided. The oxidation protection layer is a non-electrolytic metallic coating or an organic oxidation protection film on the surface of bonding finger pads or other contacts formed by... | 07/24/2007 |
| 7220657 | Semiconductor wafer and semiconductor device provided with columnar electrodes and methods of producing the wafer and device A semiconductor wafer provided with columnar electrodes which have plated nickel, palladium, and gold films successively formed at the top thereof, or have a plated solder film at their top. The semiconductor wafer can be preferably used for producing a chip-sized s... | 05/22/2007 |
| 7112523 | Bumping process A method of forming a plurality of bumps over a wafer mainly comprises the steps of providing a wafer having a plurality of bonding pads, forming an adhesive layer on the surface of the wafer to cover the bonding pads, patterning the adhesive layer to expose the bon... | 09/26/2006 |
| 6664129 | Integrated circuits and methods for their fabrication To fabricate contacts on a wafer backside, openings (124) are formed in the face side of the wafer (104). A dielectric layer (140) and some contact material (150), e.g. metal, are deposited into the openings. Then the backside is etched until the contacts... | 12/16/2003 |
| 6653738 | Semiconductor device The semiconductor device has a backside electrode disposed on a backside of the semiconductor substrate and including multiple layers of metal. The backside electrode includes, on the semiconductor substrate, a first layer of aluminum, a second layer of b... | 11/25/2003 |
| 6639303 | Integrated circuits and methods for their fabrication To fabricate back side contact pads that are suitable for use in a vertical integrated circuit, vias are made in the face side of a wafer, and dielectric and contact pad metal are deposited into the vias. Then the wafer back side is etched until the metal... | 10/28/2003 |
| 6426242 | Semiconductor chip packaging method A method of packaging a chip made in a semiconductor wafer. The method includes providing, on a first surface of the wafer, a conductive area extending beyond the periphery of the chip; adding a first thick plate including an electrically isolating materi... | 07/30/2002 |
| 6346432 | Semiconductor element having external connection terminals, method of manufacturing the semiconductor element, and semiconductor device equipped with the semiconductor element External connection terminals (25) are disposed on side surfaces, a back surface, or both the side surfaces and the back surface of a semiconductor element, especially an optical element (20) such as an image sensor, a solid state imaging device, etc. The... | 02/12/2002 |
| 6232655 | Semiconductor element having external connection terminals, method of manufacturing the semiconductor element, and semiconductor device equipped with the semiconductor element External connection terminals (25) are disposed on side surfaces, a back surface, or both the side surfaces and the back surface of a semiconductor element, especially an optical element (20) such as an image sensor, a solid state imaging device, etc. The... | 05/15/2001 |
| 6222266 | Miniaturization of a semiconductor chip A source electrode, gate electrode, drain electrode, and a gate bus bar connected to said gate electrode are formed on a semiconductor chip. A field effect transistor unit constructed on the semiconductor chip is made up of three adjacent fingers each ext... | 04/24/2001 |
| 6156165 | Method of forming a metallization feature on an edge of an IC chip An integrated circuit package derives increased mechanical robustness and electrical reliability consistent with increased heat dissipation capacity by edge bonding of integrated circuit chips onto a substrate such as a chip, board, module or another inte... | 12/05/2000 |
| 6075279 | Semiconductor device In a semiconductor device of the present invention, since a second semiconductor substrate is provided wherein a part of a semiconductor device in which an active device is formed is utilized as electrodes and third electrodes are formed on a surface of t... | 06/13/2000 |
| 6059939 | Method for high density edge mounting of chips An integrated circuit package derives increased mechanical robustness and electrical reliability consistent with increased heat dissipation capacity by edge bonding of integrated circuit chips onto a substrate such as a chip, board, module or another inte... | 05/09/2000 |
| 5903437 | High density edge mounting of chips An integrated circuit package derives increased mechanical robustness and electrical reliability consistent with increased heat dissipation capacity by edge bonding of integrated circuit chips onto a substrate such as a chip, board, module or another inte... | 05/11/1999 |
| 5731635 | Semiconductor device having a carrier and a multilayer metallization A semiconductor device has a carrier, at least one semiconductor component provided on this carrier, and a multilayer metallization between the semiconductor component and the carrier. A first metal layer of aluminium, gold, or a gold alloy is provided on... | 03/24/1998 |
| 5533664 | Method of manufacturing a semiconductor device In bonding the connecting electrodes of adjacent semiconductor chips to each other, a solder layer shaped like a bump is formed on that portion of the connecting electrode which is positioned on the upper surface of the semiconductor chip. The semiconduct... | 07/09/1996 |
| 5512776 | Interdigitated IMPATT devices A monolithic circuit including an IMPATT with the IMPATT formed as a plurality of parallel vertical fingers or an array of vertical mesas having a common doped region to apread the area for heat dissipation through the substrate.... | 04/30/1996 |
| 5231302 | Semiconductor device including an oblique surface and an electrode crossing the oblique surface A semiconductor device is made by etching a III-V compound semiconductor layer having a (100) surface using a mask having an opening defined by edges including at least one edge along an [011] direction of the layer so that the surface revealed by etching... | 07/27/1993 |
| 5018002 | High current hermetic package including an internal foil and having a lead extending through the package lid and a packaged semiconductor chip A hermetic semiconductor chip package includes a conductive foil bonded to a contact pad of the chip and connected to an external lead of the package through an aperture in the insulating material of the package lid.... | 05/21/1991 |
| 4896194 | Semiconductor device having an integrated circuit formed on a compound semiconductor layer A semiconductor device includes a Si substrate, a compound semiconductor layer selectively formed on one main surface of the Si substrate, a hole formed in the Si substrate to expose a portion of a back surface of the compound semiconductor layer, a micro... | 01/23/1990 |
| 4882608 | Multilayer semiconductor device having multiple paths of current flow A multilayer semiconductor structure is disclosed having a plurality of conducting layers separated by a barrier layer. A common contact extends from an upper exposed surface to all the layers of the device and a surface contact extends from the upper sur... | 11/21/1989 |
| 4812886 | Multilayer contact apparatus and method A multilayer contact is shown in a heterojunction device. One contact extends through two or more vertical, conducting layers. Two contacts deposited on a common surface. Each contact separately bias different layers beneath the surface. A Schottky barrie... | 03/14/1989 |
| 4596070 | Interdigitated IMPATT devices The disclosure relates to a semiconductor substrate having an active area for formation of an IMPATT device which is formed as a plurality of separated fingers having a common n+ region to spread the area over which the IMPATT is disposed and which provid... | 06/24/1986 |
| 4587547 | Electrode structure for a semiconductor devices An electrode structure for use in semiconductor devices comprising: a semiconductive layer; a conductive layer disposed on one surface of the semiconductive layer; first regions which intervene between the layers and serve as passages for transmitting min... | 05/06/1986 |
| 4349394 | Method of making a zener diode utilizing gas-phase epitaxial deposition A method of making a Zener diode having a Zener voltage in the range of 2.4-3.3 volts. The PN junction is preferably formed by selective epitaxial deposition of P-type silicon on a previously oxidized N-type silicon wafer in an opened region where the oxi... | 09/14/1982 |
| 4321613 | Field effect devices and their fabrication A method of fabricating a field effect transistor comprising the steps of forming an active layer of semiconductor material, e.g. GaAs over the surface of a first substrate of semiconductor material, e.g., also GaAs, forming source, drain and gate electro... | 03/23/1982 |
| 4237600 | Method for fabricating stacked semiconductor diodes for high power/low loss applications A semiconductor wafer is appropriately doped to create a P-N or P-I-N junction, and metallized on both its planar surfaces with electrode material. The wafer is then bonded to a second similarly processed wafer. Without damaging the semiconductor material... | 12/09/1980 |
| 4219827 | Integrated circuit with metal path for reducing parasitic effects An integrated circuit comprises a semiconductor body with a metal path running at least partially on the component side surface of the semiconductor body itself. The invention also includes the method of making the arrangement.... | 08/26/1980 |
| 4097890 | Low parasitic capacitance and resistance beamlead semiconductor component and method of manufacture A beamlead semiconductor component and a method for manufacturing the semiconductor device with low parasitic capacitance and electrical resistance is provided. The beamlead component includes a thick layer of glass forming one end of the component direct... | 06/27/1978 |
| 4075650 | Millimeter wave semiconductor device A mesa semiconductor device, including a metal film conductor located on the upper surface of the device about the base of the mesa to reduce skin effect loss.... | 02/21/1978 |
