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| Number | Title | Issue Date |
| 7442619 | Method of forming substantially L-shaped silicide contact for a semiconductor device A method of manufacturing a semiconductor device having a substantially L-shaped silicide element forming a contact is disclosed. The substantially L-shaped silicide element, inter alia, reduces contact resistance and may allow increased density of CMOS circuits. In... | 10/28/2008 |
| 7442642 | Method of forming electrode for semiconductor device The semiconductor device of the present invention and the method of the present invention, for forming the semiconductor device, form: a penetrating hole in a semiconductor wafer which has a first insulating film and an electrode pad formed on a first face of the se... | 10/28/2008 |
| 7435993 | High temperature, high voltage SiC void-less electronic package An electronic package designed to package silicon carbide discrete components for silicon carbide chips. The electronic package allows thousands of power cycles and/or temperature cycles between −55° C. to 300° C. The present invention can also tolerate continuo... | 10/14/2008 |
| 7436069 | Semiconductor device, having a through electrode semiconductor module employing thereof and method for manufacturing semiconductor device having a through electrode The layout density of the through electrodes in the horizontal plane of the substrate is enhanced. Through holes 103 extending through the silicon substrate 101 is provided. An insulating film 105 is buried within the through hole 103. A ... | 10/14/2008 |
| 7425759 | Semiconductor chip assembly with bumped terminal and filler A semiconductor chip assembly includes a semiconductor chip that includes a conductive pad, a conductive trace that includes a routing line, a bumped terminal and a filler, a connection joint that electrically connects the routing line and the pad, and an encapsulan... | 09/16/2008 |
| 7420281 | Stacked chip semiconductor device A stacked chip semiconductor device whose size is substantially reduced by high density packaging of two or more semiconductor chips. In the semiconductor device, four semiconductor chips are stacked over a printed wiring board. The bottom semiconductor chip has an ... | 09/02/2008 |
| 7414301 | Printed circuit board with soldering lands The present invention provides a printed circuit board having an area of non-resist portion, where each non-resist portion expands gradually toward the back end of a land array in the dipping direction A. Thus the area of solder deposition also expands in the region... | 08/19/2008 |
| 7411294 | Display device having misalignment detection pattern for detecting misalignment between conductive layer and insulating layer A display device includes a display panel, and the circuit substrate is separately formed and positioned different from the array substrate of the display panel and connected to the display panel. The circuit substrate includes an insulating substrate, a conductive ... | 08/12/2008 |
| 7411285 | Low profile stacked semiconductor chip package A stacked semiconductor chip package comprising a first semiconductor chip having an upper surface, a lower surface opposed to said upper surface, and a plurality of conductive metal lines formed on said upper surface of said first semiconductor chip; a plurality of... | 08/12/2008 |
| 7405485 | Semiconductor device A semiconductor device provided with a first semiconductor chip having a first functional surface formed with a first functional element and a first rear surface, a second semiconductor chip having a second functional surface which is formed with a second functional... | 07/29/2008 |
| 7405459 | Semiconductor device comprising porous film The present invention provides a zeolite sol which can be formed into a porous film that can be thinned to an intended thickness by a method used in the ordinary semiconductor process, that excels in dielectric properties, adhesion, film consistency and mechanical s... | 07/29/2008 |
| 7405473 | Techniques for optimizing electrical performance and layout efficiency in connectors with via placement and routing Techniques are provided for placing and routing vias that conduct signals through a connector between two electrical units. Vias that conduct a first set of signals are placed next to vias that provide return paths for the first set of signals to reduce cross-talk o... | 07/29/2008 |
| 7405474 | Low cost thermally enhanced semiconductor package In one embodiment, a device is packaged using a low-cost thermally enhanced ball grid array (LCTE-BGA) package. The device may include a die with its backside mounted to the bottom side of a multi-layer packaging substrate. Thermal vias may be formed through the sub... | 07/29/2008 |
| 7397125 | Semiconductor device with bonding pad support structure A semiconductor device having bonding pads on a semiconductor substrate includes: an upper copper layer that is formed on the lower surface of the bonding pads with a barrier metal interposed and that has a copper area ratio that is greater than layers in which circ... | 07/08/2008 |
| 7385283 | Three dimensional integrated circuit and method of making the same A three dimensional integrated circuit structure includes at least first and second devices, each device comprising a substrate and a device layer formed over the substrate, the first and second devices being bonded together in a stack, wherein the bond between the ... | 06/10/2008 |
| 7381591 | Flip-chip adaptor package for bare die A board for connecting a bare semiconductor die with a bond pad arrangement which does not conform to a master printed circuit board with a specific or standardized pin out, connector pad, or lead placement arrangement. The board comprises a printed circuit board in... | 06/03/2008 |
| 7361988 | Apparatuses and methods to route line to line Various methods and apparatuses are described in which a printed circuit board has trace lines. Input/output pads on the printed circuit board may have approximately the same width dimension as a trace line connected to those input/output pads. A first group of vias... | 04/22/2008 |
| 7358602 | Semiconductor chip, and semiconductor wafer including a variable thickness insulating layer A semiconductor chip includes: a semiconductor substrate; a penetrating electrode which is formed through the semiconductor substrate from a first surface to a second surface of the semiconductor substrate and has a projection which projects from the second surface;... | 04/15/2008 |
| 7358116 | Substrate conductive post formation A substrate with at least one conductive post formed prior to the formation of an inter-layer dielectric (ILD) coating on the substrate. The conductive post may be formed from a metal layer of the substrate. Additionally, the conductive post may be built up on the s... | 04/15/2008 |
| 7355267 | Substrate, semiconductor die, multichip module, and system including a via structure comprising a plurality of conductive elements A method of forming a multiconductor via includes forming at least one seed layer in at least one through-hole of a substrate, selectively patterning the seed layer to form a plurality of laterally separated regions, and depositing metal upon the regions. Alternativ... | 04/08/2008 |
| 7352059 | Low loss interconnect structure for use in microelectronic circuits A low loss on-die interconnect structure includes first and second differential signal lines on one of the metal layers of a microelectronic die. One or more traces may also be provided on another metal layer of the die that are non-parallel (e.g., orthogonal) to th... | 04/01/2008 |
| 7351653 | Method for damascene process Disclosed are methods for carrying out a damascene process in semiconductor fabrication including the steps of: forming an intermetal dielectric film on a semiconductor substrate; patterning the intermetal dielectric film and forming an intermetal dielectric pattern... | 04/01/2008 |
| 7335977 | Semiconductor chip mounting arrangement Disclosed is a device which comprises a substrate, a plurality of signal output terminal electrodes provided on the substrate, a plurality of signal input terminal electrodes provided on the substrate, and a display driver IC having input terminals thereof connected... | 02/26/2008 |
| 7329945 | Flip-chip adaptor package for bare die A board for connecting a bare semiconductor die with a bond pad arrangement which does not conform to a master printed circuit board with a specific or standardized pin out, connector pad, or lead placement arrangement. The board comprises a printed circuit board in... | 02/12/2008 |
| 7329946 | I/O architecture for integrated circuit package A circuit package may include an upper surface of first conductive elements and second conductive elements. The first conductive elements may receive input/output signals from respective conductive elements of an integrated circuit die, and the second conductive ele... | 02/12/2008 |
| 7323784 | Top via pattern for bond pad structure Top via pattern for a bond pad structure has at least one first via group and at least one second via group adjacent to each other. The first via group has at least two line vias extending in a first direction. The second via group has at least two line vias extendi... | 01/29/2008 |
| 7312523 | Enhanced via structure for organic module performance A circuit board comprises a resin-filled plated (RFP) through-hole; a dielectric layer over the RFP through-hole; a substantially circular RFP cap in the dielectric layer and connected to an upper opening of the RFP through-hole; a via stack in the dielectric layer;... | 12/25/2007 |
| 7300879 | Methods of fabricating metal wiring in semiconductor devices Manufacturing costs may be reduced and yield may be improved when metal wiring in a semiconductor device is fabricated by a disclosed method including: sequentially forming an etch stop layer, an intermetal insulation layer, an anti-reflection coating layer, and a m... | 11/27/2007 |
| 7301229 | Electrostatic discharge (ESD) protection for integrated circuit packages An integrated circuit package includes a package substrate with a plurality of pins coupled to a semiconductor chip having a plurality of bond pads, some of which are ic bond pads coupled to an integrated circuit formed on the semiconductor chip and others of which ... | 11/27/2007 |
| 7298035 | Semiconductor device and a method of assembling a semiconductor device A semiconductor device includes a substrate having first and second surfaces, the substrate having an opening; a first adhesive layer provided on the first surface; a second adhesive layer provided under the second surface; a third adhesive layer provided around the... | 11/20/2007 |
| 7298030 | Structure and method of making sealed capped chips A method of making a plurality of sealed assemblies is provided which includes a) assembling a first element to a second element so that a bottom surface of the first element faces downwardly toward a front surface of the second element and a top surface of the firs... | 11/20/2007 |
| 7285862 | Electronic parts packaging structure in which a semiconductor chip is mounted on a wiring substrate and buried in an insulation film The present invention includes the steps of forming a first resin film uncured on a wiring substrate including a wiring pattern, burying an electronic parts having a connection terminal on an element formation surface in the first resin film uncured in a state where... | 10/23/2007 |
| 7282794 | Multiple die stack apparatus employing t-shaped interposer elements Multiple integrated circuit devices in a stacked configuration that use a spacing element for allowing increased device density and increased thermal conduction or heat removal for semiconductor devices and the methods for the stacking thereof are disclosed. ... | 10/16/2007 |
| 7282784 | Methods of manufacture of a via structure comprising a plurality of conductive elements and methods of forming multichip modules including such via structures A method of forming a multiconductor via includes forming at least one seed layer in at least one through-hole of a substrate, selectively patterning the seed layer to form a plurality of laterally separated regions, and depositing metal upon the regions. Alternativ... | 10/16/2007 |
| 7279364 | Flip-chip adaptor package for bare die A board for connecting a bare semiconductor die with a bond pad arrangement which does not conform to a master printed circuit board with a specific or standardized pin out, connector pad, or lead placement arrangement. The board comprises a printed circuit board in... | 10/09/2007 |
| 7276787 | Silicon chip carrier with conductive through-vias and method for fabricating same A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic... | 10/02/2007 |
| 7273807 | Method for fabricating semiconductor device by forming damascene interconnections A method for fabricating a semiconductor device, in which a sufficient misalignment margin is obtained when forming interconnections and contact holes, is provided. Dielectric layer patterns which define recesses in which damascene interconnections are to be formed,... | 09/25/2007 |
| 7274101 | Semiconductor package and method for manufacturing the same A semiconductor package includes: a first substrate including: a semiconductor base material having a first side and a second side; a functional element that is provided at the first side of the semiconductor base material; a first wiring; a pad that is electrically... | 09/25/2007 |
| 7271491 | Carrier for wafer-scale package and wafer-scale package including the carrier A carrier for use in a chip-scale package, including a semiconductor substrate, such as a semiconductor wafer, with a plurality of apertures formed therethrough. The present invention also includes a chip-scale package including the carrier. When the carrier is empl... | 09/18/2007 |
| 7256497 | Semiconductor device with a barrier layer and a metal layer This invention provides a semiconductor device that can minimize deterioration of electric characteristics of the semiconductor device while minimizing the amount of etching required. In the semiconductor device of the invention, a pad electrode layer formed of a fi... | 08/14/2007 |
