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| Number | Title | Issue Date |
| 7423283 | Strain-silicon CMOS using etch-stop layer and method of manufacture Recesses are formed in the drain and source regions of an MOS transistor. An ohmic contact layer is formed in the recesses, and a stressed silicon-nitride layer is formed over the ohmic contact layer. The recesses allow the stressed silicon nitride layer to provide ... | 09/09/2008 |
| 7413968 | Method of manufacturing semiconductor device having gate electrodes of polymetal gate and dual-gate structure A silicon film is formed on a first region and a second region, respectively of a semiconductor substrate; P-type impurities are selectively ion-implanted into the silicon film in the first region; a first annealing is carried out, thereby the P-type impurities impl... | 08/19/2008 |
| 7402484 | Methods for forming a field effect transistor Methods for forming a field effect transistor are disclosed. An illustrated method comprises: forming a gate electrode on a substrate; and forming a nitride layer on at least a part of the gate electrode and the substrate. ... | 07/22/2008 |
| 7361932 | Semiconductor device and method for fabricating the same A semiconductor device of a dual-gate structure including a P-channel type field-effect transistor formed at a first region of a substrate and an N-channel type field-effect transistor formed at a second region of the substrate, includes a gate electrode including a... | 04/22/2008 |
| 7282402 | Method of making a dual strained channel semiconductor device According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. ... | 10/16/2007 |
| 7268064 | Method of forming polysilicon layer in semiconductor device Disclosed herein is a method of forming a polysilicon film of a semiconductor device. Upon deposition process of a polysilicon film, the inflow of a gas is reduced to 150 sccm to 250 sccm to control abnormal deposition depending upon excessive inflow of the gas. Acc... | 09/11/2007 |
| 7151299 | Semiconductor device and its manufacturing method The present invention provides a semiconductor device structure and an easy-to-use method for manufacturing thereof enabling to suppress wafer contamination and to form the semiconductor device superior in control and uniformity of the film thickness in the semicond... | 12/19/2006 |
| 7151055 | Technique for forming a gate electrode by using a hard mask The anisotropic etch process for forming circuit elements such as a gate electrode is accomplished by using a hard mask instead of a resist feature, thereby avoiding a complex resist trim process when critical dimensions are required, which are well below the resolu... | 12/19/2006 |
| 6696345 | Metal-gate electrode for CMOS transistor applications Described is a CMOS transistor structure with a multi-layered gate electrode structure and a method of fabrication. The gate electrode structure has a three-layered metallic gate electrode and a polysilicon layer. The first metallic layer acts as a barrie... | 02/24/2004 |
| 6664196 | Method of cleaning electronic device and method of fabricating the same An electronic device having a component containing a refractory metal such as tungsten is cleaned by using a cleaning solution composed of an acidic solution which does not substantially contain aqueous hydrogen peroxide or an alkaline solution which does... | 12/16/2003 |
| 6664195 | Method for forming damascene metal gate The present invention relates to a method of forming a damascene gate electrode of highly integrated MOS transistor capable of easily removing a dummy polysilicon layer. The disclosed comprises the steps of forming a dummy gate insulating layer and a poly... | 12/16/2003 |
| 6660577 | Method for fabricating metal gates in deep sub-micron devices A method for fabricating metal gates in deep sub-micron CMOS devices. The method blanket deposits a transition metal nitride layer on top of a gate dielectric layer for forming gate electrodes for both a PMOS and an NMOS device. After a cap layer is depos... | 12/09/2003 |
| 6645818 | Method to fabricate dual-metal gate for N- and P-FETs A new method for forming a dual-metal gate CMOS transistors is described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A nitride layer is deposited overlying a gate dielectric layer and patterned to form ... | 11/11/2003 |
| 6642575 | MOS transistor with vertical columnar structure A field-effect transistor has a vertical columnar structure to restrain a short channel effect without impairing the operating speed of an element. In a semiconductor device having a field-effect transistor with a vertical columnar structure, an n-type di... | 11/04/2003 |
| 6642090 | Fin FET devices from bulk semiconductor and method for forming The present invention thus provides a device structure and method for forming fin Field Effect Transistors (FETs) that overcomes many of the disadvantages of the prior art. Specifically, the device structure and method provides the ability to form finFET ... | 11/04/2003 |
| 6639288 | Semiconductor device with a particular conductor arrangement A tungsten nitride (6b) is provided also on side surface of a tungsten (6c), to increase an area where the tungsten (6c) and the tungsten nitride (6b) are in contact with each other. On a gate insulating film (2), a polysilicon side wall (5) having high a... | 10/28/2003 |
| 6635522 | Method of forming a MOS transistor in a semiconductor device and a MOS transistor fabricated thereby Methods of forming a MOS transistor and a MOS transistor fabricated thereby are provided. The MOS transistor includes a semiconductor substrate of a first conductivity type, and an insulated gate pattern having sidewalls disposed on a predetermined region... | 10/21/2003 |
| 6624043 | Metal gate CMOS and method of manufacturing the same A metal gate complementary metal oxide semiconductor (CMOS) and a method of manufacturing the same is disclosed. The method includes depositing the metal gate electrode material as a final step before metallization of the device. Accordingly, the metal ga... | 09/23/2003 |
| 6613626 | Method of forming CMOS transistor having a deep sub-micron mid-gap metal gate A CMOS transistor is formed on a single crystal silicon substrate. Active regions are formed on the substrate, including an nMOST active region and a pMOST active region. An epitaxial layer of undoped silicon is formed over the active regions. Out-diffusi... | 09/02/2003 |
| 6599781 | Solid state device A method of mass-producing a solid state device comprises supplying a solid state material substrate; providing two adjacent semiconductor pockets on the substrate; and forming a gate layer less than 3 to 40 Angstroms thick. The gate layer has atomically ... | 07/29/2003 |
| 6593229 | Semiconductor integrated circuit device and method for manufacturing the same Described is a manufacturing method for a semiconductor integrated circuit device which comprises forming, over a gate insulating film which has been formed over the main surface of a single crystal silicon substrate to have an effective film thickness le... | 07/15/2003 |
| 6592771 | Vapor-phase processing method and apparatus therefor A method in which etching or ashing is conducted by providing satisfactory kinetic energy of reaction seeds such as ions or radicals without damaging a substrate, and an apparatus used in this method are provided. A predetermined film of for example polyc... | 07/15/2003 |
| 6537901 | Method of manufacturing a transistor in a semiconductor device There is disclosed a method of manufacturing a transistor in a semiconductor device. The present invention forms a Ta film or a TaNx film at a low temperature or forms a first TaNx film in which the composition(x) of nitrogen is 0.45~0.55, on a gate insul... | 03/25/2003 |
| 6511872 | Device having a high dielectric constant material and a method of manufacture thereof The present invention provides a method of manufacturing a semiconductor device. The method includes depositing a metal oxide containing a dopant and having a high dielectric constant on a substrate; wherein the metal is aluminum or silicon and the dopant... | 01/28/2003 |
| 6509609 | Grooved channel schottky MOSFET A grooved channel Schottky contacted MOSFET has asymmetric source and drain regions. The MOSFET includes an undoped silicon substrate with a background doping concentration of less than about 1017 cm-3. A grooved channel is formed in... | 01/21/2003 |
| 6506639 | Method of forming low resistance reduced channel length transistors Methods of manufacturing semiconductor devices having low resistance reduced channel length transistors. Spacers are formed on each side of trenches that define the location of transistor channels. The spacers are formed with a dimension between the space... | 01/14/2003 |
| 6492249 | High-K gate dielectric process with process with self aligned damascene contact to damascene gate and a low-k inter level dielectric A method of fabricating a transistor having shallow source and drain extensions utilizes a self-aligned contact. The drain extensions are provided through an opening between a contact area and the gate structure. A high-K gate dielectric material can be u... | 12/10/2002 |
| 6468888 | Method for forming polysilicon-germanium gate in CMOS transistor and device made thereby A method for making a ULSI MOSFET chip includes forming transistor gates on a substrate and a semiconductor device thereby made. The gates are formed by depositing a polysilicon layer on the substrate, implanting germanium into the polysilicon layer at a ... | 10/22/2002 |
| 6429052 | Method of making high performance transistor with a reduced width gate electrode and device comprising same The present invention is directed to a method for manufacturing a high performance transistor device with a reduced width or "t-shaped" gate electrode. The method disclosed herein comprises forming a gate insulation layer on a semiconducting substrate, fo... | 08/06/2002 |
| 6392280 | Metal gate with PVD amorphous silicon layer for CMOS devices and method of making with a replacement gate process A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a physical vapor deposited (PVD) layer of amorphous silicon on the high k gate dielec... | 05/21/2002 |
| 6380014 | Manufacture method of semiconductor device with suppressed impurity diffusion from gate electrode A method of manufacturing a semiconductor device includes the step of forming a MOS transistor structure on a semiconductor substrate, the MOS transistor structure having an insulated gate electrode. The method further includes the step of depositing a si... | 04/30/2002 |
| 6373113 | Nitrogenated gate structure for improved transistor performance and method for making same An integrated circuit is provided in which nitrogen is incorporated into the gate dielectric and transistor gate. A method for forming the integrated circuit preferably comprises the providing of a semiconductor substrate that has a p-well and a laterally... | 04/16/2002 |
| 6362511 | MIS-type semiconductor device having a multi-portion gate electrode In A MIS type semiconductor device using a polycrystalline silicon film as a gate electrode, a lower portion of the polycrystalline silicon film has larger grains in average diameter than an upper portion thereof, and there is no peak of oxygen concentrat... | 03/26/2002 |
| 6346450 | Process for manufacturing MIS transistor with self-aligned metal grid This invention relates to a MIS transistor and its manufacturing process. The process comprises the following steps: a) production of a dummy grid on a substrate, made of a material capable of resisting heat treatment, b) formation of self-aligned source and d... | 02/12/2002 |
| 6232164 | Process of making CMOS device structure having an anti-SCE block implant A method of fabricating a CMOS device having (1) an anti-SCE block region below a channel region and (2) a metal gate. The invention uses a masking layer having an opening to define the anti-SCE block implant and also the gate structure. The method compri... | 05/15/2001 |
| 6207483 | Method for smoothing polysilicon gate structures in CMOS devices There is provided a method for smoothing the surface of undoped polysilicon regions of a CMOS structure, primarily gate regions. A direct HPD-CVD argon sputter is used improve the surface roughness by a factor of more than 50%. The argon plasma sputter ma... | 03/27/2001 |
| 6207991 | Integrated non-volatile and CMOS memories having substantially the same thickness gates and methods of forming the same A method of forming non-volatile memory (e.g., an EEPROM device) and a CMOS device (e.g., a RAM), on a single die or chip, and a structure formed by the method. In one embodiment, the control gate of the storage transistor as well as the isolation gate of... | 03/27/2001 |
| 6165826 | Transistor with low resistance tip and method of fabrication in a CMOS process A novel transistor with a low resistance ultra shallow tip region and its method of fabrication in a complementary metal oxide semiconductor (CMOS) process. According to the preferred method of the present invention, a first gate dielectric and a first ga... | 12/26/2000 |
| 6137177 | CMOS semiconductor device There is provided a method of fabricating a CMOS semiconductor device including nMOSFET and pMOSFET, including the steps of (a) forming a gate insulating film on a semiconductor substrate, (b) forming a first polysilicon film on the gate insulating film, ... | 10/24/2000 |
| 6114208 | Method for fabricating complementary MOS transistor A method for fabricating complementary metal-oxide-semiconductor (CMOS) devices and circuits resulting therefrom are provided. The method includes forming the source and drain regions of the CMOS device by out-diffusion of ions injected into a conductive ... | 09/05/2000 |
