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| Number | Title | Issue Date |
| 7442640 | Semiconductor device manufacturing methods Methods of manufacturing a semiconductor device including a high-voltage device region and a low-voltage device region are provided. An illustrated method includes forming, on a substrate, a gate pattern for a high-voltage device and a low-voltage device; implanting... | 10/28/2008 |
| 7419905 | Gate electrodes and the formation thereof A method of fabricating a gate electrode for a semiconductor comprising the steps of: providing a substrate; providing on the substrate a layer of a first material of thickness tp, the first material being selected from the group consisting of Si, Si... | 09/02/2008 |
| 7410852 | Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistors An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a sour... | 08/12/2008 |
| 7396724 | Dual-hybrid liner formation without exposing silicide layer to photoresist stripping chemicals Methods of fabricating a semiconductor device including a dual-hybrid liner in which an underlying silicide layer is protected from photoresist stripping chemicals by using a hard mask as a pattern during etching, rather than using a photoresist. The hard mask preve... | 07/08/2008 |
| 7368353 | Trench power MOSFET with reduced gate resistance A method for manufacturing a trench type power semiconductor device which includes process steps for forming proud gate electrodes in order to decrease the resistivity thereof. ... | 05/06/2008 |
| 7332420 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device having a P-type MOSFET and an N-type MOSFET, the method comprising the steps of: forming a gate insulating film, a non-doped polysilicon film, a metal silicide film, a metal nitride film and a metal film on a semicon... | 02/19/2008 |
| 7320914 | System and method for gate formation in a semiconductor device A method for forming a memory device is provided. A first layer is formed over a substrate. A second layer is formed over the first layer. A mask is formed over the second layer. Spacers are formed adjacent opposite sides of the mask. The second layer is etched to f... | 01/22/2008 |
| 7306990 | Information storage element, manufacturing method thereof, and memory array An information memory device capable of reading and writing of information by mechanical operation of a floating gate layer, in which a gate insulation film has a cavity (6), and a floating gate layer (5) having two stable deflection states in the cavi... | 12/11/2007 |
| 7208409 | Integrated circuit metal silicide method Fluorine containing regions (70) are formed in the source and drain regions (60) of the MOS transistor. A metal layer (90) is formed over the fluorine containing regions (70) and the source and drain regions (60). The metal layer i... | 04/24/2007 |
| 7202132 | Protecting silicon germanium sidewall with silicon for strained silicon/silicon germanium MOSFETs Raised Si/SiGe source and drain regions include epitaxially grown silicon on SiGe sidewalls. The epi silicon prevents adverse effects of Ge during silicidation, including Ge out diffusion and silicide line breakage. The Si also increases the active area. ... | 04/10/2007 |
| 7179702 | Semiconductor device including metal insulator semiconductor field effect transistor and method of manufacturing the same A semiconductor device comprises a semiconductor substrate, an N-channel MISFET and a P-channel MISFET provided on the semiconductor substrate, each of the N- and P-channel MISFETs being isolated by an isolation region and having a gate insulating film, a first gate... | 02/20/2007 |
| 7172967 | Methods for forming cobalt layers including introducing vaporized cobalt precursors and methods for manufacturing semiconductor devices using the same The present invention provides methods for forming cobalt silicide layers, including introducing a vaporized cobalt precursor onto a silicon substrate to form a cobalt layer. The vaporized cobalt precursor has the formula Co2(CO)6(R1... | 02/06/2007 |
| 7118954 | High voltage metal-oxide-semiconductor transistor devices and method of making the same A method for fabricating metal-oxide-semiconductor devices is provided. The method includes forming a gate dielectric layer on a substrate; depositing a polysilicon layer on the gate dielectric layer; forming a resist mask on the polysilicon layer; etching the polys... | 10/10/2006 |
| 6686617 | Semiconductor chip having both compact memory and high performance logic A process for fabrication of both compact memory and high performance logic on the same semiconductor chip. The process comprises forming a memory device in the memory region, forming a spacer nitride layer and a protective layer over both the memory regi... | 02/03/2004 |
| 6683352 | Semiconductor device structure A metal oxide semiconductor field effect transistor structure is disclosed. A p-shape gate, disposed over a semiconductor substrate. A gate dielectric layer is disposed in between the p-shape gate and the semiconductor substrate. A drain region is dispose... | 01/27/2004 |
| 6677234 | Method of selectively forming silicide In a crystalline silicon body a shallow trench insulation is made by etching a groove and filling it with silicon oxide. Ridges of polysilicon are made on the surface of the silicon body by applying a layer of polysilicon and patterning it with a known te... | 01/13/2004 |
| 6642093 | Method for manufacturing a semiconductor device According to the present invention, a method for manufacturing a semiconductor device forms a cobalt silicide film 11 on source/drain regions 7a and 7b and a gate electrode 4 of transistors in the logic circuit region, making it possible to form a high-pe... | 11/04/2003 |
| 6633059 | Semiconductor device having MOS transistor A p type well region, a field insulation film, a gate insulation film, and a gate-use poly-Si layer are formed on the surface of a silicon substrate, after which a laminate of a silicon nitride layer and a resist layer is used as a mask in ion implantatio... | 10/14/2003 |
| 6569743 | Method of fabricating a semiconductor device A method of fabricating a semiconductor device is provided. In this method, a gate insulating layer and a gate are sequentially formed on a semiconductor substrate of a first conductivity type. A first active region of a second conductivity type is formed... | 05/27/2003 |
| 6566213 | Method of fabricating multi-thickness silicide device formed by disposable spacers A transistor device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The device includes a gate defin... | 05/20/2003 |
| 6531736 | Semiconductor device and method of manufacturing thereof In the manufacture of a semiconductor device having a logic section and a memory section built in the same chip, a thin layer of refractory metal (titanium: Ti) is deposited by sputtering in the logic section with the entire memory section covered with a ... | 03/11/2003 |
| 6514824 | Semiconductor device with a pair of transistors having dual work function gate electrodes Techniques are described for fabricating a pair of ଲ-identical transistors, in other words, a pair of transistors whose dimensions and electrical characteristics, other than their respective gate electrode work functions, are substantially similar. ... | 02/04/2003 |
| 6512296 | Semiconductor structure having heterogenous silicide regions having titanium and molybdenum A process for forming heterogeneous silicide structures on a semiconductor substrate (10) includes implanting molybdenum ions into selective areas of the semiconductor substrate (10) to form molybdenum regions (73, 74, 75, 76). Titanium is then deposited ... | 01/28/2003 |
| 6504195 | Alternate method for photodiode formation in CMOS image sensors A complementary metal oxide semiconductor (CMOS) active pixel sensor (APS) having a plurality of pixels which includes at least one pixel entailing a photodetector, a transistor adjacent the photodetector having a silicide surface, and an insulator over t... | 01/07/2003 |
| 6468857 | Method for forming a semiconductor device having a plurality of circuits parts Provided are a semiconductor device in which a MOS transistor of SAC structure and a MOS transistor of salicide structure are provided together, and a method of manufacturing the same. Each gate electrode (3) of gate structures (GT11 to GT13) is covered w... | 10/22/2002 |
| 6468904 | RPO process for selective CoSix formation A method for forming an improved RPO layer by using a composite layer and a two-step etching process in a salicide process in the fabrication of integrated circuits is described. Isolation areas are formed on a semiconductor substrate surrounding and elec... | 10/22/2002 |
| 6468867 | Method for forming the partial salicide This invention relates to a method for forming the salicide, more particularly, to the method for forming the salicide in the partial region. The present invention uses a nitride layer to be the mask layer to form the salicide in the partial region of the... | 10/22/2002 |
| 6391750 | Method of selectively controlling contact resistance by controlling impurity concentration and silicide thickness Methods are provided that selectively provide various contact resistances based on each individual transistor's influence on an overall chip speed during the formation of active regions and silicide layers. In order to provide lower contact resistance to ... | 05/21/2002 |
| 6383903 | Method for forming the partial salicide This invention relates to a method for forming the salicide, more particularly, to the method for forming the salicide in the partial region. The present invention uses an oxide layer to be the mask layer to form the salicide in the partial region of the ... | 05/07/2002 |
| 6383882 | Method for fabricating MOS transistor using selective silicide process A method for fabricating a MOS transistor using a selective silicide process wherein a gate insulating layer and a gate polysilicon layer are sequentially formed on a silicon substrate, and a gate spacer is formed on a side wall of the gate insulating lay... | 05/07/2002 |
| 6376351 | High Fmax RF MOSFET with embedded stack gate A method for forming a wide gate stack over a gate in a rf device is described. The invention reduces the gate resistance and the Rs significantly. A substrate has a digital area and a rf area. Devices used in digital circuits will be formed in the digita... | 04/23/2002 |
| 6376348 | Reliable polycide gate stack with reduced sheet resistance and thickness Formation of a gate having a polysilicon and silicide layer thereover with reduced resistance and reduced thickness is provided. The polysilicon layer is annealed to diffuse the dopants out from the surface to reduce the dopant concentration to below the ... | 04/23/2002 |
| 6335236 | Manufacturing method of semiconductor device A manufacturing method of a semiconductor device obtaining performances respectively required in a MOS transistor in semiconductor memories and a MOS transistor in logic devices even in case of manufacturing a system LSI combining the semiconductor memori... | 01/01/2002 |
| 6329287 | Process for manufacturing an integrated circuit structure with metal salicide regions and metal salicide exclusion regions A process for the formation of metal salicide regions and metal salicide exclusion regions in an integrated circuit (IC) that requires a minimum number of steps and is compatible with standard MOS processing techniques. In the process, an IC structure is ... | 12/11/2001 |
| 6303443 | Method of fabricating salicide in electrostatic discharge protection device A method of fabricating a salicide layer in an electrostatic discharge protection device. On a MOS transistor having a gate, a source region and a drain region, a salicide block layer is formed. The salicide layer is patterned to remaining covering the dr... | 10/16/2001 |
| 6299314 | Semiconductor device with electrical isolation means Provided are a semiconductor device in which a MOS transistor of SAC structure and a MOS transistor of silicide structure are are provided together, and a method of manufacturing the same. Each gate electrode (3) of gate structures (GT11 to GT13) is cover... | 10/09/2001 |
| 6291279 | Method for forming different types of MOS transistors on a semiconductor wafer A semiconductor wafer has a substrate, a first region in the substrate that is used for a logic circuit, and a second region in the substrate that is used for a memory cell. A first gate in the first region and a second gate in the second region are simul... | 09/18/2001 |
| 6287911 | Semiconductor device with silicide layers and fabrication method thereof A semiconductor device is provided, which is capable of high-speed operation of MOSFETs in a device section while suppressing the current leakage of MOSFETs in another device section even if the device is further miniaturized. This device is comprised of ... | 09/11/2001 |
| 6287913 | Double polysilicon process for providing single chip high performance logic and compact embedded memory structure A process for fabrication of both compact memory and high performance logic on the same semiconductor chip. The process comprises forming a memory device in the memory region, forming a spacer nitride layer and a protective layer over both the memory regi... | 09/11/2001 |
| 6281067 | Self-aligned silicide process for forming silicide layer over word lines in DRAM and transistors in logic circuit region A self-aligned process for forming a silicide layer over word lines in DRAM and a silicide layer over transistors in a logic device region. A substrate that includes a memory cell region and a logic circuit region is provided. A first transistor and a sec... | 08/28/2001 |
