Class 257/E21.609 - Comprising combination of vertical and lateral transistors (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.608. This subclass
No. of patents: 33
Last issue date: 07/03/2007

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Number	Title	Issue Date
7238576	Semiconductor device and method of manufacturing the same A semiconductor device comprises a drain layer of first conductivity type, drift layers of first and second conductivity types on the drain layer, an insulating film between the drift layers and contacting the drift layers, a first base layer of second conductivity ...	07/03/2007
7119384	Field effect transistor and method for fabricating it The invention relates to a field effect transistor in which the planar channel region on the upper surface of the elevation is extended in width by means of additional vertical channel regions on the lateral surfaces of the elevation. Said additional vertical channe...	10/10/2006
6610578	Methods of manufacturing bipolar transistors for use at radio frequencies A bipolar transistor of type NPN has an active region at the surface of the component, which is surrounded, as seen along the surface of the component, in the conventional way by thick field oxide areas. The active region is partly covered by an electrica...	08/26/2003
6573146	Methods of manufacturing complementary bipolar transistors A complementary bipolar transistor having a lateral npn bipolar transistor, a vertical and a lateral pnp bipolar transistor, an integrated injection logic, a diffusion capacitor, a polysilicon capacitor and polysilicon resistors are disclosed. The lateral...	06/03/2003
6518139	Power semiconductor device structure with vertical PNP transistor A power semiconductor device structure formed in a chip of semiconductor material includes an N-type substrate and an N-type epitaxial layer. The structure comprises a P-type insulation region which forms a pocket in which control circuitry is formed, and...	02/11/2003
6326674	Integrated injection logic devices including injection regions and tub or sink regions A complementary bipolar transistor having a lateral npn bipolar transistor, a vertical and a lateral pnp bipolar transistor, an integrated injection logic, a diffusion capacitor, a polysilicon capacitor and polysilicon resistors are disclosed. The lateral...	12/04/2001
6291303	Method for manufacturing a bipolar junction device A method of forming an improved bipolar junction device structure. By forming a well region around the emitter terminal, the area of distribution of ions within the emitter terminal of a vertical bipolar junction transistor is enlarged. Furthermore, by fo...	09/18/2001
6150225	Method for fabricating a semiconductor device having vertical and lateral type bipolar transistors A semiconductor device has a P type semiconductor substrate 1, a vertical type bipolar transistor having an N type base region 4, a lateral type bipolar transistor having an N type base region 4 formed on the semiconductor substrate 1, an N type collector...	11/21/2000
6005283	Complementary bipolar transistors A complementary bipolar transistor having a lateral npn bipolar trasistor, a vertical and a lateral pnp bipolar transistor, an integrated injection logic, a diffusion capacitor, a polysilicon capacitor and polysilicon resistors are disclosed. The lateral ...	12/21/1999
6005284	Semiconductor device and its manufacturing method A bipolar semiconductor device includes an npn transistor using a base outlet electrode in the form of a polycrystalline Si film and one or more other devices using an electrode in the form of a polycrystalline Si film supported on a common p-type Si subs...	12/21/1999
5693543	Method of manufacturing a semiconductor IIL device with dielectric and diffusion isolation n type epitaxial layers are formed on the main surface of a p type semiconductor substrate. A field oxide film is selectively formed in the surface of n type epitaxial layers. An n type diffusion region is formed in n type epitaxial layers positioned dire...	12/02/1997
5481130	Semiconductor IIL device with dielectric and diffusion isolation n type epitaxial layers are formed on the main surface of a p type semiconductor substrate. A field oxide film is selectively formed in the surface of n type epitaxial layers. An n type diffusion region is formed in n type epitaxial layers positioned dire...	01/02/1996
5376565	Fabrication of lateral bipolar transistor A process for forming a lateral bipolar transistor wherein apertures for forming a current electrode (collector or emitter) region, a base region and an isolation region are all formed simultaneously so that they are automatically aligned. Also, a mask ar...	12/27/1994
5254486	Method for forming PNP and NPN bipolar transistors in the same substrate In one embodiment, this method forms PNP and NPN transistors in a same epitaxial layer. The P-type regions for both the PNP and the NPN transistors are initially defined using a single masking step. Therefore, the emitter and collector region pattern for ...	10/19/1993
5198375	Method for forming a bipolar transistor structure A vertical bipolar transistor (10) and a lateral bipolar transistor (11) are formed wherein both transistors (10 and 11) have a substrate (12). A dielectric layer (22) is formed overlying the substrate (12), and a conductive layer (24) is formed overlying...	03/30/1993
5179432	Integrated PNP power bipolar transistor with low injection into substrate In one embodiment of the invention, a P buried region is formed in an N epitaxial layer and isolated from a P substrate by an N buried region. P+ emitters and P+ collectors are formed in the surface of the N epitaxial layer (acting as a base). The P burie...	01/12/1993
5163178	Semiconductor device having enhanced impurity concentration profile A semiconductor device comprises a semiconductor substrate provided with a collector region a base region and an emitter region in a lateral arrangement. Respective portions having peak impurity concentrations of the collector region and the emitter regio...	11/10/1992
5070381	High voltage lateral transistor The described embodiments of the present invention provide a structure and method for easily incorporating a high voltage lateral bipolar transistor in an integrated circuit. A buried base contact is formed and the base itself is formed of a well region i...	12/03/1991
4978630	Fabrication method of bipolar transistor Present invention relates to the fabrication method of the bipolar transistor which includes NPN transistor and field-plate lateral PNP transistor. The arsenic implanted polycrystalline silicon is used for the emitter electrode of NPN transistor to increa...	12/18/1990
4961102	Junction programmable vertical transistor with high performance transistor An oxide-isolated RAM and PROM process is disclosed wherein a RAM circuit includes a lateral PNP transistor formed in the same island of silicon material as a vertical NPN device and further wherein contact is made to the base of the lateral PNP and to th...	10/02/1990
4804634	Integrated circuit lateral transistor structure In a monolithic silicon integrated circuit fast diffusing impurities are incorporated into the collectors of the bipolar lateral transistors. The impurity level is controlled, using ion implantation, so that after device processing the lateral transistor ...	02/14/1989
4624046	Oxide isolation process for standard RAM/PROM and lateral PNP cell RAM An oxide-isolated RAM and PROM process is disclosed wherein a RAM circuit includes a lateral PNP transistor formed in the same island of silicon material as a vertical NPN device and further wherein contact is made to the base of the lateral PNP and to th...	11/25/1986
4583106	Fabrication methods for high performance lateral bipolar transistors The lateral transistor is described which has both its base width and the emitter region of the transistor minimized. This minimization of the elements of the lateral transistor gives high performance. The lateral transistor which may be typically PNP tra...	04/15/1986
4566174	Semiconductor device and method for manufacturing the same A method of manufacturing a semiconductor device wherein a pair of grooves having different depths are formed in a surface of a semiconductor substrate, an epitaxial layer of one conductivity type is grown to a depth enough to fill a shallower one of the ...	01/28/1986
4546536	Fabrication methods for high performance lateral bipolar transistors The lateral transistor is described which has both its base width and the emitter region of the transistor minimized. This minimization of the elements of the lateral transistor gives high performance. The lateral transistor which may be typically PNP tra...	10/15/1985
4510676	Method of fabricating a lateral PNP transistor A method for making a lateral PNP transistor simultaneously with an NPN transistor and the resultant device wherein a first mask defines a base-width by the resistor implant for a P-type resistor and a second mask is overlaid asymmetrically on said first ...	04/16/1985
4492008	Methods for making high performance lateral bipolar transistors A high performance lateral transistor may be fabricated by first providing a monocrystalline semiconductor body having a principal surface and where the desired transistor is a PNP transistor, a buried N+ region with an N+ reach-through connecting the bur...	01/08/1985
4378630	Process for fabricating a high performance PNP and NPN structure Disclosed is the fabrication and structure of very small integrated circuit devices of both PNP and NPN types with very high speeds and low power requirements. The structure provides vertical NPN and lateral PNP transistors formed within the same semicond...	04/05/1983
4339767	High performance PNP and NPN transistor structure Disclosed is the fabrication and structure of very small integrated circuit devices of both PNP and NPN types with very high speeds and low power requirements. The structure provides vertical NPN and lateral PNP transistors formed within the same semicond...	07/13/1982
4326212	Structure and process for optimizing the characteristics of I² L devices An improved I2 L structure and process are disclosed which reduces the minority carrier charge storage, increases the emitter injection efficiency and reduces the emitter diffusion capacitance in the upward injecting vertical NPN transistor and...	04/20/1982
4264382	Method for making a lateral PNP or NPN with a high gain utilizing reactive ion etching of buried high conductivity regions A method for making lateral PNP or NPN devices in isolated monocrystalline silicon pockets wherein silicon dioxide isolation surrounds the pocket and partially, below the surface, within the isolated monocrystalline region. The P emitter or N emitter diff...	04/28/1981
4025364	Process for simultaneously fabricating epitaxial resistors, base resistors, and vertical transistor bases A process for simultaneously fabricating epitaxial resistors, base resistors, and vertical transistor bases in a semiconductor substrate utilizes the stopping power of different layers of materials to determine the location of impurity concentrations indu...	05/24/1977
3945857	Method for fabricating double-diffused, lateral transistors A double-diffused, lateral transistor structure is fabricated utilizing an etch resistant mask to provide self-aligning positional accuracy for formation of active areas of the transistor. The lateral structure includes semiconductor material having at le...	03/23/1976

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Class 257/E21.609 - Comprising combination of vertical and lateral transistors (EPO)