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| Number | Title | Issue Date |
| 7439125 | Contact structure for a stack DRAM storage capacitor A method for fabricating a contact structure for a stack storage capacitor includes forming the contact structure in a node contact region with contact openings, an insulating liner and a conductive filling material prior to the patterning of bit lines. ... | 10/21/2008 |
| 7435676 | Dual damascene process flow enabling minimal ULK film modification and enhanced stack integrity Interconnect structures possessing an organosilicate glass interlayer dielectric material with minimal stoichiometeric modification and optionally an intact organic adhesion promoter for use in semiconductor devices are provided herein. The interconnect structure is... | 10/14/2008 |
| 7436009 | Via structures and trench structures and dual damascene structures Via hole and trench structures and fabrication methods are disclosed. The structure includes a conductive layer in a dielectric layer, and a via structure in the dielectric layer contacting a portion of a surface of the conductive layer. The via structure includes t... | 10/14/2008 |
| 7435685 | Method of forming a low-K dual damascene interconnect structure A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is the... | 10/14/2008 |
| 7435677 | Method for fabricating semiconductor device A method for fabricating a semiconductor device includes: forming a first inter-layer insulation layer over a substrate where a plurality of first contact holes are formed; forming a conductive layer over the first inter-layer insulation layer to fill the first cont... | 10/14/2008 |
| 7432200 | Filling narrow and high aspect ratio openings using electroless deposition Methods of fabricating an interconnect utilizing an electroless deposition technique, which fundamentally consists of providing a dielectric material layer having an opening extending into the dielectric material from a first surface thereof, and electrolessly depos... | 10/07/2008 |
| 7422942 | Method for fabricating a semiconductor device having an insulation film with reduced water content A semiconductor device having a self-aligned contact hole is formed by providing a side wall oxide film on a gate electrode, covering the gate electrode and the side wall oxide film by an oxide film and further covering the oxide film by a nitride film, wherein the ... | 09/09/2008 |
| 7417321 | Via structure and process for forming the same Via structure and process flow for interconnection in a semiconductor product. A bottom metal layer is provided to represent a connection layer in the semiconductor product. An isolation layer on the bottom metal layer comprises a via hole exposing a portion of the ... | 08/26/2008 |
| 7417319 | Semiconductor device with connecting via and dummy via and method of manufacturing the same An underlying interconnect including a first barrier metal layer, an interconnect metal layer and a second barrier metal layer is formed on a semiconductor substrate, and an interlayer dielectric is formed thereon. Etching is performed with a photoresist defining an... | 08/26/2008 |
| 7416973 | Method of increasing the etch selectivity in a contact structure of semiconductor devices By providing an additional silicon dioxide based etch stop layer, a corresponding etch process for forming contact openings for directly connecting polysilicon lines and active areas may be controlled in a highly reliable manner. In another aspect, the etch selectiv... | 08/26/2008 |
| 7416987 | Semiconductor device and method of fabricating the same According to the present invention, there is a provided a semiconductor device fabrication method having, forming a mask material in a surface portion of a semiconductor substrate, and forming a step having a projection by using the mask material; forming a dielectr... | 08/26/2008 |
| 7411210 | Semiconductor probe with resistive tip having metal shield thereon A semiconductor probe with a resistive tip and a method of fabricating the semiconductor probe. The resistive tip doped with a first impurity includes a resistive region formed at a peak thereof and lightly doped with a second impurity opposite in polarity to the fi... | 08/12/2008 |
| 7410896 | Semiconductor device having low-k dielectric film in pad region and method for manufacture thereof A low-k dielectric film is formed on an entire surface of a substrate having a pad region and a circuit region. A resist pattern is formed on the low-k dielectric film, and an opening is formed in the low-k dielectric film of the pad region using the resist pattern ... | 08/12/2008 |
| 7410881 | Method of manufacturing flash memory device A method of manufacturing a flash memory device includes etching an insulating layer provided over a substrate to form a contact hole to define a contact hole exposing a junction region formed on the substrate. The contact hole is filled with a first conductive mate... | 08/12/2008 |
| 7411301 | Semiconductor integrated circuit device In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried... | 08/12/2008 |
| 7405153 | Method for direct electroplating of copper onto a non-copper plateable layer A process for the formation of an interconnect in a semiconductor structure including the steps of forming a dielectric layer on a substrate, forming a first barrier layer on the dielectric layer, forming a second barrier layer on the first barrier layer, wherein th... | 07/29/2008 |
| 7402515 | Method of forming through-silicon vias with stress buffer collars and resulting devices A method of forming a via having a stress buffer collar, wherein the stress buffer collar can absorb stress resulting from a mismatch in the coefficients of thermal expansion of the surrounding materials. Other embodiments are described and claimed. ... | 07/22/2008 |
| 7393784 | Method of manufacturing suspension structure and chamber A method of manufacturing a suspension structure including providing a substrate, forming a hole and a sacrificial layer filling the hole on the substrate, forming a patterned photoresist layer on the substrate and the sacrificial layer, the patterned photoresist la... | 07/01/2008 |
| 7393779 | Shrinking contact apertures through LPD oxide Sublithographic contact apertures through a dielectric are formed in a stack of dielectric, hardmask and oxide-containing seed layer. An initial aperture through the seed layer receives a deposition of oxide by liquid phase deposition, which adheres selectively to t... | 07/01/2008 |
| 7384816 | Apparatus and method for forming vias An apparatus and method for forming vias in one or more layers, comprising one or more beams located in alignment with the layers for forming one or more vias in one or more areas of the layers. A vacuum mechanism is provided for collecting ablated material caused b... | 06/10/2008 |
| 7381645 | Method for the production of an integrated circuit bar arrangement comprising a metal nitride layer and integrated circuit arrangement The document explains, inter alia, a method in which a titanium nitride layer is removed by wet chemical means (106). Following removal of the titanium nitride, further metalization strata are produced (114). The result is an integrated circuit arrange... | 06/03/2008 |
| 7375028 | Method for manufacturing a semiconductor device A semiconductor device may be manufactured by a method that includes forming an etch stop layer on a semiconductor substrate, sequentially forming a first interlayer insulating layer, a first diffusion barrier, a second interlayer insulating layer, and a second diff... | 05/20/2008 |
| 7375430 | Semiconductor device and method of manufacture thereof A semiconductor device includes a semiconductor substrate having a first surface. First gate electrodes are formed along a first direction on the first surface. Source/drain areas are formed in the first surface and sandwich a channel region. A first interlayer insu... | 05/20/2008 |
| 7375004 | Method of making an isolation trench and resulting isolation trench A method of forming and resulting isolation region, which allows for densification of an oxide layer in the isolation region. One exemplary embodiment of the method includes the steps of forming a first trench, forming an oxide layer on the bottom and sidewalls of t... | 05/20/2008 |
| 7371659 | Substrate laser marking A method for forming a feature in a substrate, where residue within the feature can be easily removed. An upper sidewall portion of the feature is formed, where the upper sidewall portion forms a void in the substrate. The upper sidewall portion has an upper sidewal... | 05/13/2008 |
| 7365009 | Structure of metal interconnect and fabrication method thereof A process and structure for a metal interconnect includes providing a substrate with a first electric conductor, forming a first dielectric layer and a first patterned hard mask, using the first patterned hard mask to form a first opening and a second electric condu... | 04/29/2008 |
| 7365413 | Reduced power distribution mesh resistance using a modified swiss-cheese slotting pattern Electrical interconnects with a slotting pattern are provided in the present invention. In addition, the masks for making such interconnects and semiconductor devices incorporating such interconnects are also provided in the present invention. The slotting pattern m... | 04/29/2008 |
| 7361992 | Semiconductor device including interconnects formed by damascene process and manufacturing method thereof After etching the interlayer dielectric film 4 formed on the lower layer interconnect line 1 into a shape with holes, the upper layer dielectric film 6 is etched into a shape with trenches utilizing the etching stopper 5. The etching stop... | 04/22/2008 |
| 7358612 | Plasma treatment at film layer to reduce sheet resistance and to improve via contact resistance A method of manufacturing a semiconductor device contact including forming an insulating layer over a substrate and forming an agglutinating layer over the insulating layer. The agglutinating layer is then exposed to a plasma treatment. A barrier layer is formed ove... | 04/15/2008 |
| 7354867 | Etch process for improving yield of dielectric contacts on nickel silicides The embodiments of the invention generally relate to an etching process, and more particularly to an etch processing for improving the yield of dielectric contacts on nickel silicides. An oxygen-free feedgas is used in an etching process to reduce or eliminate resid... | 04/08/2008 |
| 7354799 | Methods for anchoring a seal ring to a substrate using vias and assemblies including an anchored seal ring Disclosed are embodiments of a method for forming a seal ring on a substrate that is anchored to the substrate by a number of vias. Also disclosed are embodiments of an assembly including such an anchored seal ring. In some embodiments, a seal ring may extend around... | 04/08/2008 |
| 7351609 | Method for wafer level package of sensor chip A method for wafer level package (WLP) of sensor chips is provided, including the steps of: providing a wafer, the wafer including a plurality of die regions, each the die region on a first surface of the wafer comprising an active area and a pad surrounding the act... | 04/01/2008 |
| 7344959 | Metal filled through via structure for providing vertical wafer-to-wafer interconnection A method of fabricating a through via connection useful in providing a vertical wafer-to-wafer interconnect structure is provided as well as the vertical interconnect structure that is formed by this method. The method of the present invention using only a metal stu... | 03/18/2008 |
| 7344976 | Method for fabricating nonvolatile semiconductor memory device An adhesion layer composed of a titanium film and a titanium nitride film is formed by CVD on the inner wall of a contact hole formed in a multilayer film composed of an interlayer insulating film, a silicon nitride film, and a silicon dioxide film. Then, a conducti... | 03/18/2008 |
| 7344977 | Method of electroplating a substance over a semiconductor substrate The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a si... | 03/18/2008 |
| 7341886 | Apparatus and method for forming vias A method and apparatus for forming vias in one or more layers, comprising providing a vacuum chamber, one or more beams in the vacuum chamber. The array of directed beams located in alignment with a layer for ablating one or more areas of the layer for forming vias.... | 03/11/2008 |
| 7341943 | Post etch copper cleaning using dry plasma A method for post-etch copper cleaning uses a hydrogen plasma with a trace gas additive constituting about 3-10 percent of the plasma by volume to clean a copper surface exposed by etching. The trace gas may be atomic nitrogen or other species having an atomic mass ... | 03/11/2008 |
| 7342286 | Electrical node of transistor and method of forming the same According to example embodiments of the present invention, there are provided an electrical node of a transistor and a method of forming the same, which may reduce or minimize current leakage between the electrical node and a semiconductor substrate when a buried co... | 03/11/2008 |
| 7341941 | Methods to facilitate etch uniformity and selectivity A semiconductor device is fabricated with energy based process(es) that alter etch rates for dielectric layers within damascene processes. A first interconnect layer is formed over a semiconductor body. A first dielectric layer is formed over the first interconnect ... | 03/11/2008 |
| 7339274 | Metallization performance in electronic devices Phenomena such as electromigration and stress-induced migration occurring in metal interconnects of devices such as integrated circuits are inhibited by use of underlying non-planarities. Thus the material underlying the interconnect is formed to have non-planaritie... | 03/04/2008 |
