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| Number | Title | Issue Date |
| 7427565 | Multi-step etch for metal bump formation The present invention uses a two step plasma etch process to create a via contact with an integral bump. After the via and bump have been plated, the semiconductor substrate is planarized to remove the excess metal, using the semiconductor substrate as a planar stop... | 09/23/2008 |
| 7419847 | Method for forming metal interconnection of semiconductor device A method for forming a metal interconnection of a semiconductor device avoids over-etching and under-etching through the use of the “self-stop” function of a nitridation layer, to prevent the occurrence of openings and voids in a copper interconnection and to ob... | 09/02/2008 |
| 7413975 | Interconnect substrate, semiconductor device, methods of manufacturing the same, circuit board, and electronic equipment A first conductive layer is formed. An insulating layer is formed so that at least a part of the insulating layer is disposed on the first conductive layer. A second conductive layer is formed so that at least a part of the second conductive layer is disposed on the... | 08/19/2008 |
| 7411305 | Interconnect structure encased with high and low k interlevel dielectrics A structure for improving the electrostatic discharge robustness of an integrated circuit having an electrostatic discharge (ESD) device and a receiver network connected to a pad by interconnects. The interconnect between the pad and the ESD device has a high-k mate... | 08/12/2008 |
| 7396703 | Method of making a semiconductor chip assembly with a bumped terminal and a filler A method of making a semiconductor chip assembly includes providing a metal base, a routing line, a bumped terminal and a filler, wherein the routing line contacts the bumped terminal and the filler, then mechanically attaching a semiconductor chip to the metal base... | 07/08/2008 |
| 7396759 | Protection of Cu damascene interconnects by formation of a self-aligned buffer layer Methods of protecting exposed metal damascene interconnect surfaces in a process for making electronic components and the electronic components made according to such methods. An integrated circuit structure having damascene regions with exposed metal surfaces is pr... | 07/08/2008 |
| 7387957 | Fabrication process for a semiconductor integrated circuit device In a fabrication process of a semiconductor integrated circuit device, upon effecting connection of an interconnection made of aluminum or aluminum alloy and another interconnection made of Cu or Cu alloy, a barrier conductor film or plug is disposed at the joint po... | 06/17/2008 |
| 7381638 | Fabrication technique using sputter etch and vacuum transfer First material (106) is situated on the surface of a substructure (100 and 102) and in an opening (104), such as a Wench, that extends partway through the substructure. Second material (108) is situated on the first material in the... | 06/03/2008 |
| 7372154 | Semiconductor device As etch-stop films or Cu-diffusion barrier films used in insulation films constituting conductor layers of a stacked structure, films having smaller dielectric constant than silicon nitride films are used, and an insulation film at a lower-layer part of the stacked ... | 05/13/2008 |
| 7361582 | Method of forming a damascene structure with integrated planar dielectric layers Methods are provided for forming a circuit component on a workpiece substrate. The methods comprise the steps of depositing a dielectric material over the substrate; etching a pattern through the dielectric material to expose a portion of the substrate; depositing a... | 04/22/2008 |
| 7361596 | Semiconductor processing methods The invention includes methods of forming titanium-containing materials, such as, for example, titanium silicide. The invention can use alternating cycles of titanium halide precursor and one or more reductants to form the titanium-containing material. For instance,... | 04/22/2008 |
| 7344976 | Method for fabricating nonvolatile semiconductor memory device An adhesion layer composed of a titanium film and a titanium nitride film is formed by CVD on the inner wall of a contact hole formed in a multilayer film composed of an interlayer insulating film, a silicon nitride film, and a silicon dioxide film. Then, a conducti... | 03/18/2008 |
| 7341945 | Method of fabricating semiconductor device A method of fabricating a semiconductor device prevents agglomeration of a seed metal layer in a recess. A recess is formed in a dielectric layer formed on or over a wafer. A seed metal layer (e.g., Cu or Cu alloy) is then formed on a bottom face and an inner side f... | 03/11/2008 |
| 7335580 | Lamellar-derived microelectronic component array and method of fabrication Sub-lithographic lamella and pillar structures defined by larger lines or lamellae are described. A static random access memory (SRAM) cell structure is created in a three-dimensional format as a vertical stack of wired transistors. These transistors are fabricated ... | 02/26/2008 |
| 7335587 | Post polish anneal of atomic layer deposition barrier layers A method for forming a semiconductor device is disclosed wherein atomic layer deposition (ALD) precursor species and/or by-product absorbed by an ILD are outgassed and/or neutralized prior to subsequently patterning the semiconductor device, thereby improving the ab... | 02/26/2008 |
| 7332422 | Method for CuO reduction by using two step nitrogen oxygen and reducing plasma treatment A method for cleaning a copper interconnect after a chemical-mechanical polishing that comprises: a) treating the surface of said copper interconnect with a nitrogen and oxygen containing treatment; and b) without breaking vacuum, treating the copper interconnect wi... | 02/19/2008 |
| 7323409 | Method for forming a void free via A multilevel metal and via structure is described. The metal conductors include a base or seed layer, a bulk conductor layer, a capping layer, and a barrier layer, and the via structure include a seed layer, a diffusion barrier layer and a metal plug. The via... | 01/29/2008 |
| 7323785 | Semiconductor device A through-electrode that penetrates a semiconductor substrate and that is insulatively separated from the semiconductor substrate includes an inner through-electrode, a quadrangular ring-shaped semiconductor, and an outer peripheral through-electrode. The quadrangul... | 01/29/2008 |
| 7320934 | Method of forming a contact in a flash memory device A method of forming a contact between a bitline and a local interconnect in a flash memory device comprises forming a hard mask layer on a planarized surface that includes an exposed top section of the local interconnects prior to depositing an oxide dielectric laye... | 01/22/2008 |
| 7315084 | Copper interconnection and the method for fabricating the same A copper interconnection where holes in the vicinity of an interface are reduced to lower contribution of interface diffusion to Cu the EM, increase a lifetime, and simultaneously increase adhesiveness and resistance to stress migration is constituted in a manner th... | 01/01/2008 |
| 7314811 | Method to make corner cross-grid structures in copper metallization A new method to prevent cracking at the corners of a semiconductor die during dicing is described. Dummy metal structures are fabricated at the corners of the die to prevent cracking. The design for the dummy metal structures can be generated automatically by a comp... | 01/01/2008 |
| 7312141 | Shapes-based migration of aluminum designs to copper damascene An interconnect structure, method of fabricating the interconnect structure and method of designing the interconnect structure for use in semiconductor devices. The interconnect structure includes a damascene metal wire having a pattern of dielectric filled holes. | 12/25/2007 |
| 7309920 | Chip structure and process for forming the same A chip or wafer comprises a semiconductor substrate, first and second transistors on the semiconductor substrate, first and second metal layers over the semiconductor substrate, an insulating layer on the first and second metal layers, a third and fourth metal layer... | 12/18/2007 |
| 7306977 | Method and apparatus for facilitating signal routing within a programmable logic device Method and apparatus for facilitating signal routing within a programmable logic device having routing resources is described. In an example, the routing resources are formed into groups where, for each of the groups, the routing resources are of a same type. Pairs ... | 12/11/2007 |
| 7303986 | Semiconductor device and a method of manufacturing the same An insulating portion of the respective wiring layers for a semiconductor device is constituted of insulating films. The one insulating film is made of a material whose conductivity is higher than that of the other insulating film that is made of an ordinary silicon... | 12/04/2007 |
| 7300861 | Method for interconnecting electronic components using a blend solution to form a conducting layer and an insulating layer An improved method of interconnecting electronic devices is described. In the method a blended material for forming a conducting layer and an insulating layer are deposited between a contact of a first electronic device and a second electronic device. The blended ma... | 11/27/2007 |
| 7288475 | Sacrificial inorganic polymer intermetal dielectric damascene wire and via liner The present invention provides a method of forming a rigid interconnect structure, and the device therefrom, including the steps of providing a lower metal wiring layer having first metal lines positioned within a lower low-k dielectric; depositing an upper low-k di... | 10/30/2007 |
| 7288481 | Semiconductor device having through electrode and method of manufacturing the same With a fluid insulating material applied on a convex substrate and a fluid insulating material applied on a concave substrate, a columnar conductive portion of the convex substrate is inserted into a hole of the concave substrate. With this, a conductive portion and... | 10/30/2007 |
| 7285853 | Multilayer anti-reflective coating for semiconductor lithography and the method for forming the same An interconnect structure has a dielectric layer having a dielectric constant less than 3.9 overlying a substrate with a conductive region, a silicon oxycarbide layer overlying the dielectric layer, and a silicon oxynitride layer overlying the silicon oxycarbide lay... | 10/23/2007 |
| 7265433 | On-pad broadband matching network A chip is provided in which an on-chip matching network has a first terminal conductively connected to a bond pad of the chip and a second terminal conductively connected to a common node on the chip. A wiring trace connects the on-chip matching network to a circuit... | 09/04/2007 |
| 7262134 | Microfeature workpieces and methods for forming interconnects in microfeature workpieces Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. In one embodiment, a method of forming an interconnect in a microfeature workpiece includes forming a hole extending through a t... | 08/28/2007 |
| 7253521 | Methods for making integrated-circuit wiring from copper, silver, gold, and other metals Integrated circuits include networks of electrical components that are typically wired, or interconnected, together with aluminum wires. In recent years, researchers have begun using copper in combination with diffusion barriers, rather than aluminum, to form the wi... | 08/07/2007 |
| 7253093 | Method for fabricating interconnection in an insulating layer on a wafer A method for fabricating an interconnection in an insulating layer on a wafer is described. A wafer having a plurality of conductive lines thereon is provided. An insulating layer is formed over the conductive lines. Two via holes are formed in the insulating layer ... | 08/07/2007 |
| 7247552 | Integrated circuit having structural support for a flip-chip interconnect pad and method therefor A technique for alleviating the problems of defects caused by stress applied to bond pads (32) includes, prior to actually making an integrated circuit (10), adding dummy metal lines (74, 76) to interconnect layers (18, 22, 26) to increas... | 07/24/2007 |
| 7247562 | Semiconductor element, semiconductor device and methods for manufacturing thereof The present invention provides a method of manufacturing a semiconductor element having a miniaturized structure and a semiconductor device in which the semiconductor element having a miniaturized structure is integrated highly, by overcoming reduction of the yield ... | 07/24/2007 |
| 7244642 | Method to obtain fully silicided gate electrodes The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises depositing a protective layer (510) over a spacer material (415) located over gate electrodes (250) and a doped region (255 | 07/17/2007 |
| 7238606 | Semiconductor devices and method for fabricating the same Methods for fabricating a copper interconnect of a semiconductor device are disclosed. An example method for fabricating a copper interconnect of a semiconductor device deposits a first insulating layer on a substrate having at least one predetermined structure, for... | 07/03/2007 |
| 7232746 | Method for forming dual damascene interconnection in semiconductor device A method for forming a dual damascene interconnection in a semiconductor device, which is capable of preventing a lower metal film from being corroded. The method includes the steps of forming an etch stop film and an intermetal insulating film sequentially on a low... | 06/19/2007 |
| 7232749 | Integrated circuit inductane and the fabrication method thereof An integrated circuit inductance and the fabrication method thereof are disclosed. The manufacture process provided by the present invention fabricates an integrated circuit inductance having a simple production process, low cost, a near equal loop size and good per... | 06/19/2007 |
| 7233071 | Low-k dielectric layer based upon carbon nanostructures A low-k dielectric material for use in the manufacture of semiconductor devices, semiconductor structures using the low-k dielectric material, and methods of forming such dielectric materials and fabricating such structures. The low-k dielectric material comprises c... | 06/19/2007 |
