Class 257/E21.564 - SOI together with lateral isolation, e.g., using local oxidation of silicon, or dielectric or polycrystalline material refilled trench or air gap isolation regions, e.g., completely isolated semiconductor islands (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.561. This subclass
No. of patents: 652
Last issue date: 09/09/2008

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Number	Title	Issue Date
7423323	Semiconductor device with raised segment A device having a raised segment, and a manufacturing method for same. An SOI wafer is provided having a substrate, an insulating layer disposed over the substrate, and a layer of semiconductor material disposed over the insulating layer. The semiconductor material ...	09/09/2008
7393738	Subground rule STI fill for hot structure This invention provides a hybrid orientation (HOT) semiconductor-on-insulator (SOI) structure having an isolation region, e.g. a shallow trench isolation region (STI), and a method for forming the STI structure that is easy to control. The method of forming the isol...	07/01/2008
7393731	Semiconductor device and method of manufacturing the same A silicon nitride film is formed between interlayer insulating films covering an upper surface of an element formed on a surface of a semiconductor layer. With this structure, a semiconductor device comprising an isolation insulating film of PTI structure, which sup...	07/01/2008
7394132	Apparatus and methods for integrated circuit with devices with body contact and devices with electrostatic discharge protection An integrated circuit (IC) includes one or more silicon-on-insulator (SOI) transistors. Each SOI transistor includes a first source region, a second source region, a drain region, a body contact region, a gate, and first and second isolation regions. The body contac...	07/01/2008
7372107	SOI chip with recess-resistant buried insulator and method of manufacturing the same A semiconductor-on-insulator structure includes a substrate and a buried insulator stack overlying the substrate. The buried insulator stack includes a first dielectric layer and a recess-resistant layer overlying the first dielectric layer. A second dielectric laye...	05/13/2008
7352049	Semiconductor device and method of manufacturing the same Plural trench isolation films are provided with portions of an SOI layer interposed therebetween in a surface of the SOI layer in a resistor region (RR) where a spiral inductor (SI) is to be provided. Resistive elements are formed on the trench isolation films, resp...	04/01/2008
7348255	Semiconductor device and method for fabricating a semiconductor device A semiconductor structure has an active region on a substrate, and recessed portions are formed at lower edges of lateral portions of the semiconductor structure. Patterned first insulation layers for device isolation are buried into the recessed portions. Second in...	03/25/2008
7332405	Method of forming alignment marks for semiconductor device fabrication A semiconductor integrated circuit is fabricated in a substrate having a semiconductor layer and an underlying insulator layer. The fabrication process includes a step of locally oxidizing the semiconductor layer to form a field oxide, during which step the semicond...	02/19/2008
7332777	STI liner for SOI structure In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer...	02/19/2008
7316957	Semiconductor device and method for manufacturing the same A semiconductor device and a method for manufacturing the same are provided. A gate insulating film is formed under a vacuum condition to prevent deterioration of reliability of the device due to degradation of a gate insulating material and to have stable operating...	01/08/2008
7309637	Method to enhance device performance with selective stress relief A structure and method of fabrication of a semiconductor device having a stress relief layer under a stress layer in one region of a substrate. In a first example, a stress relief layer is formed over a first region of the substrate (e.g., PFET region) and not over ...	12/18/2007
7297608	Method for controlling properties of conformal silica nanolaminates formed by rapid vapor deposition A method employing atomic layer deposition rapid vapor deposition (RVD) conformally deposits a dielectric material on small features of a substrate surface. The resulting dielectric film is then annealed using a high density plasma (HDP) at a temperature under 500°...	11/20/2007
7297593	Method of manufacturing a floating gate of a flash memory device A method of forming a floating gate of a flash memory device wherein a hard mask nitride film is stripped using two or more etching steps. Accordingly, a seam can be prevented when depositing a floating gate polysilicon film. Furthermore, the floating gate polysilic...	11/20/2007
7271074	Trench insulation in substrate disks comprising logic semiconductors and power semiconductors Disclosed is a layer arrangement (4b, 5b, 9b, 10, 9a, 5a, 4a) within an insulating trench, which insulates circuits with little distortion while being suitable for electrically insul...	09/18/2007
7271464	Liner for shallow trench isolation A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a silicon nitride barrier is deposited into the trench. The silicon nitride layer has a high nitrogen content ...	09/18/2007
7265017	Method for manufacturing partial SOI substrates There is closed a semiconductor device which comprises a semiconductor substrate including an SOI region where a first insulating film is buried, and a non-SOI region, the semiconductor substrate being provided with a boundary region formed between the SOI region an...	09/04/2007
7262486	SOI substrate and method for manufacturing the same The SOI substrate 1 has a supporting substrate 10, an insulating layer 20 formed on the supporting substrate 10 and a silicon layer 30 formed on the insulating layer 20. A through electrode 40 is provided in a device ...	08/28/2007
7247910	MOSFET formed on a silicon-on-insulator substrate having a SOI layer and method of manufacturing In a FET having a thin-film SOI layer, to prevent a parasitic resistance increase in source/drain regions. To realize an elevated layer to be formed on the source/drain region without using a lithography process and without a fear of a short circuit. Element-isolati...	07/24/2007
7235456	Method of making empty space in silicon To change a plurality of trenches to one flat empty space by two-dimensionally forming the trenches on the surface of a semiconductor substrate and then applying heat treatment to the semiconductor substrate. ...	06/26/2007
7208357	Template layer formation A process for forming a strained semiconductor layer. The process includes implanting ions into a semiconductor layer prior to performing a condensation process on the layer. The ions assist in diffusion of atoms (e.g. germanium) in the semiconductor layer and to in...	04/24/2007
7205208	Method of manufacturing a semiconductor device In a method of manufacturing a semiconductor device, a first trench is formed in a first region of a substrate and a second trench is formed in a second region of the substrate different from the first region. A depth of the first trench is less than that of the sec...	04/17/2007
7196421	Integrated circuit having at least one metallization level An integrated circuit is provided that includes at least one metallization level having a plurality of dummy conductors. At least one of the dummy conductors has an oriented shape made up of a plurality of non-parallel rectangles in mutual contact. In one embodiment...	03/27/2007
7154159	Trench isolation structure and method of forming the same A trench isolation structure and a method of forming a trench isolation structure are provided. The method includes providing a substrate having a trench. A polysilicon liner is formed in the trench. A dielectric layer, such as spin-on glass, is formed in the trench...	12/26/2006
7144764	Method of manufacturing semiconductor device having trench isolation The invention relates to improvements in a method of manufacturing a semiconductor device in which deterioration in a transistor characteristic is avoided by preventing a channel stop implantation layer from being formed in an active region. After patterning a nitri...	12/05/2006
7126170	MISFET for reducing leakage current A MISFET according to this invention includes: a substrate having a semiconductor layer; an active region formed in the semiconductor layer; a gate insulator formed on the active region; a gate formed on the gate insulator; and a source region and a drain region, wh...	10/24/2006
7115463	Patterning SOI with silicon mask to create box at different depths The present invention provides a method of fabricating a patterned silicon-on-insulator substrate which includes dual depth SOI regions or both SOI and non-SOI regions within the same substrate. The method of the present invention includes forming a silicon mask hav...	10/03/2006
7109129	Optimal operation of conformal silica deposition reactors Methods of forming conformal films that reduce the amount of metal-containing precursor and/or silicon containing precursor materials required are described. The methods increase the amount of film grown following each dose of metal-containing and/or silicon-contain...	09/19/2006
7091106	Method of reducing STI divot formation during semiconductor device fabrication STI divot formation is eliminated or substantially reduced by employing a very thin nitride polish stop layer, e.g., no thicker than 400 Å. The very thin nitride polish stop layer is retained in place during subsequent masking, implanting and cleaning steps to for...	08/15/2006
7075153	Grounded body SOI SRAM cell A semiconductor memory device comprising: an SOI substrate having a thin silicon layer on top of a buried insulator; and an SRAM comprising four NFETs and two PFETs located in the thin silicon layer, each the NFET and PFET having a body region between a source regio...	07/11/2006
6800917	Bladed silicon-on-insulator semiconductor devices and method of making A semiconductor device includes an elongated, blade-shaped semiconductor element isolated from a surrounding region of a semiconductor substrate by buried and side oxide layers. A polysilicon post disposed at one end of the element has a bottom portion extending thr...	10/05/2004
6696707	High voltage integrated switching devices on a bonded and trenched silicon substrate A high voltage integrated switching device includes at least one high voltage switching circuit, preferably employing DMOS technology and characterized by a breakdown voltage of at least 100 volts, on a dielectrically isolated, bonded and vertically trenc...	02/24/2004
6693325	Semiconductor device having silicon on insulator and fabricating method therefor The present invention relates to a highly integrated SOI semiconductor device and a method for fabricating the SOI semiconductor device by reducing a distance between diodes or well resistors without any reduction in insulating characteristics. The device...	02/17/2004
6682981	Stress controlled dielectric integrated circuit fabrication General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a sem...	01/27/2004
6676748	Method for manufacturing semiconductor substrate An epitaxial layer is formed on a high-resistance semiconductor substrate containing interstitial oxygen at a high concentration, and then a heat treatment is performed to the semiconductor substrate at a high temperature in an oxidizing atmosphere. Accor...	01/13/2004
6677657	High-voltage periphery A method for forming a component in a portion of a semiconductor substrate on insulator delimited by a lateral wall separated by an insulating layer from a peripheral region internal to the portion and heavily doped of a same first conductivity type as th...	01/13/2004
6673660	Method of manufacturing semiconductor element According to the present invention, a semiconductor device to use a SOI substrate performing insulation by a LOCOS method in which an oxide resistivety film provided on a silicon layer is used, includes steps of: implanting impurity in a LOCOS edge which ...	01/06/2004
6674090	Structure and method for planar lateral oxidation in active An active semiconductor device is made using planar lateral oxidation to define a core region that is surrounded by regions of buried oxidized semiconductor material in. The buried oxidized semiconductor material provides optical waveguiding, and or a def...	01/06/2004
6667226	Method and system for integrating shallow trench and deep trench isolation structures in a semiconductor device A semiconductor device and a method for constructing a semiconductor device is disclosed. A deep trench isolation structure (108) is formed proximate a surface of a semiconductor substrate (106). A deep trench plug (122) layer is deposited within the deep...	12/23/2003
6664165	Semiconductor device and fabrication method therefor There is provided a semiconductor apparatus, and a fabrication method thereof, which are improved such that a reduction in concentration at the SOI active layer is prevented, and a parasitic MOSFET is not formed even in cases where Mesa-type isolation tec...	12/16/2003
6664598	Polysilicon back-gated SOI MOSFET for dynamic threshold voltage control A method of forming a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) device is provided. The SOI MOSFET device includes a polysilicon back-gate which controls the threshold voltage of a polysilicon-containing front-g...	12/16/2003

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Class 257/E21.564 - SOI together with lateral isolation, e.g., using local oxidation of silicon, or dielectric or polycrystalline material refilled trench or air gap isolation regions, e.g., completely isolated semiconductor islands (EPO)