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| Number | Title | Issue Date |
| 7443007 | Trench isolation structure having an implanted buffer layer The present invention provides a trench isolation structure, a method of manufacture therefor and a method for manufacturing an integrated circuit including the same. The trench isolation structure (130), in one embodiment, includes a trench located within a ... | 10/28/2008 |
| 7436030 | Strained MOSFETs on separated silicon layers A method of fabricating and a structure of an IC incorporating strained MOSFETs on separated silicon layers are disclosed. N-channel field effect transistors (nFET) and P-channel FETs (pFET) are formed on the separated silicon layers, respectively. Shallow trench in... | 10/14/2008 |
| 7429519 | Method of forming isolation layer of semiconductor device A method of forming an isolation structure of a semiconductor device includes implanting dopants of a first type into a semiconductor substrate to form a doped region in the substrate. A mask layer is provided over the substrate and the doped region of the substrate... | 09/30/2008 |
| 7390717 | Trench power MOSFET fabrication using inside/outside spacers A fabrication process for a trench type power semiconductor device includes forming inside spacers over a semiconductor surface. Using the spacers as masks, trenches with gates are formed in the semiconductor body. After removing the spacers, source implants are for... | 06/24/2008 |
| 7361546 | Method of forming conductive stud on vertical memory device A method of forming a conductive stud is provided. The method includes providing a substrate which has an upper surface and an opening. The opening exposes a portion of a vertical memory device. A conductive layer is formed over the substrate to fill the opening. A ... | 04/22/2008 |
| 7358149 | Substrate isolation in integrated circuits Substrate isolation trench (224) are formed in a semiconductor substrate (120). Dopant (e.g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transis... | 04/15/2008 |
| 7339252 | Semiconductor having thick dielectric regions A method of manufacturing a semiconductor device includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The method also includes providing in the semiconductor substrate one or more trenches, first mesas and second... | 03/04/2008 |
| 7338880 | Method of fabricating a semiconductor device A method of fabricating a semiconductor device includes steps of forming at least one shallow-trench isolation region in a semiconductor substrate; forming a photoresist pattern for blocking a photodiode region; sequentially implanting dopant ions and boron ions int... | 03/04/2008 |
| 7297604 | Semiconductor device having dual isolation structure and method of fabricating the same In a semiconductor device having a dual isolation structure, and a method of fabricating the same, an epitaxial layer is formed on the entire surface of the semiconductor device. A device region including the semiconductor device and the epitaxial layer is defined b... | 11/20/2007 |
| 7279397 | Shallow trench isolation method A method (200) of forming an isolation structure is presented, in which a hard mask layer (304, 308) is formed (204, 206) over the isolation and active regions (305, 303) of a semiconductor body (306), and a dopant is selectively p... | 10/09/2007 |
| 7276411 | Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described... | 10/02/2007 |
| 7268043 | Semiconductor device and method of manufacturing the same A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gat... | 09/11/2007 |
| 7262110 | Trench isolation structure and method of formation In general, the present invention discloses at least one trench isolation region formed in a semiconductor substrate to electrically and/or optically isolate at least one active region from another active region. The at least one trench isolation region comprises a ... | 08/28/2007 |
| 7259069 | Semiconductor device and method of manufacturing the same A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gat... | 08/21/2007 |
| 7259421 | Non-volatile memory devices having trenches A semiconductor memory device includes a semiconductor substrate having a trench therein. First and second gate patterns are formed on a surface of the substrate adjacent the trench, a respective one of which is on a respective opposing side of the trench. A split s... | 08/21/2007 |
| 7244661 | Method for forming a buried diffusion layer with reducing topography in a surface of a semiconductor substrate A method for forming a buried diffusion layer with reducing topography in a surface of a semiconductor substrate is provided. A patterned first dielectric layer is formed on a semiconductor substrate for being used as a first hard mask. A thermal oxidation process i... | 07/17/2007 |
| 7238568 | Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described... | 07/03/2007 |
| 7235460 | Method of forming active and isolation areas with split active patterning A process for forming isolation and active regions, wherein the patterning of an oxidation-barrier active stack is performed separately in the PMOS and NMOS regions. After the active stack is in place, two masking steps are used: one exposes the isolation areas on t... | 06/26/2007 |
| 7232697 | Semiconductor device having enhanced photo sensitivity and method for manufacture thereof Provided are a semiconductor device and a method for its manufacture. In one example, the method includes forming an isolation structure having a first refraction index over a sensor embedded in a substrate. A first layer having a second refraction index that is dif... | 06/19/2007 |
| 7229878 | Phototransistor of CMOS image sensor and method for fabricating the same A phototransistor of a CMOS image sensor suitable for decreasing the size of layout, and a method for fabricating the phototransistor are disclosed, in which the phototransistor includes a first conductive type semiconductor substrate; an STI layer on the first cond... | 06/12/2007 |
| 7199006 | Planarization method of manufacturing a superjunction device A method of manufacturing a semiconductor device includes providing a substrate having first and second main surfaces. The substrate has a heavily doped region of a first conductivity at the second main surface and has a lightly doped region of the first conductivit... | 04/03/2007 |
| 7157328 | Selective etching to increase trench surface area The surface area of the walls of a trench formed in a substrate is increased. A barrier layer is formed on the walls of the trench such that the barrier layer is thinner near the corners of the trench and is thicker between the corners of the trench. A dopant is int... | 01/02/2007 |
| 7118956 | Trench capacitor and a method for manufacturing the same A trench capacitor comprises a semiconductor substrate, a trench, formed in the semiconductor substrate, having upper and lower portions, a first doped polysilicon layer filled in the lower portion through a first dielectric film and doped with a first impurity havi... | 10/10/2006 |
| 6686252 | Method and structure to reduce CMOS inter-well leakage A method of forming a semiconductor device with improved leakage control, includes: providing a semiconductor substrate; forming a trench in the substrate; forming a leakage stop implant in the substrate under the bottom of the trench and under and aligne... | 02/03/2004 |
| 6680239 | Effective isolation with high aspect ratio shallow trench isolation and oxygen or field implant A method for forming shallow trench isolation (STI) with a higher aspect ratio is given. This method allows the formation of narrower and deeper trench isolation regions while avoiding substrate damage due to excessive etching and severe microloading effe... | 01/20/2004 |
| 6664602 | Semiconductor device and method of manufacturing the same An object of the invention is to suppress degradation of the effective isolation width between a well and a diffusion layer caused by impurity ion implantation for forming the well performed at a predetermined incident angle. A well is formed by performin... | 12/16/2003 |
| 6656816 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device enables the formation of a well optimized for a fine MOS transistor and a well formed deep with a relatively low concentration for a high voltage MOS transistor without increasing the number of manufacturi... | 12/02/2003 |
| 6653201 | Method for forming an isolation region in a semiconductor device A method for forming an isolation region in a semiconductor device, in which nitrogen ions are injected into a region of an isolation oxide film to form an oxynitride film, thereby preventing formation of a recess at a top edge of the isolation oxide film... | 11/25/2003 |
| 6638832 | Elimination of narrow device width effects in complementary metal oxide semiconductor (CMOS) devices Neutral conductivity ions, preferably germanium, are implanted through the oxide of a metal oxide semiconductor after isolation formation to provide a nearly constant threshold voltage for transistor operation independent of transistor channel width as de... | 10/28/2003 |
| 6638805 | Method of fabricating a DRAM semiconductor device A method of fabricating a DRAM semiconductor device including forming gate stacks in which a gate pattern and a gate sacrificial mask are sequentially deposited on a semiconductor substrate, forming an etch stopper on the semiconductor substrate, forming ... | 10/28/2003 |
| 6624016 | Method of fabricating trench isolation structures with extended buffer spacers The trench-isolation structures for fabricating semiconductor devices using two different multilayer masking structures are disclosed by the present invention, in which the extended buffer spacers located in the isolation regions are formed on the sidewal... | 09/23/2003 |
| 6617217 | Reduction in well implant channeling and resulting latchup characteristics in shallow trench isolation by implanting wells through nitride Retrograde wells are formed by implanting through nitride films (40). Nitride films (40) are formed after STI (20) formation. By selectively masking a portion of the wafer with photoresist (47) after portions of a retrograde well are formed (45, 50, 55, a... | 09/09/2003 |
| 6613635 | Method of fabricating semiconductor device having element isolation trench Threshold voltage fluctuation in upper corner portions of a trench isolation is inhibited by rounding upper corner portions of the trench by thermal oxidation, introducing a first impurity into both upper corner portions of the trench and heat-treating th... | 09/02/2003 |
| 6599840 | Material removal method for forming a structure Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the materi... | 07/29/2003 |
| 6599810 | Shallow trench isolation formation with ion implantation An insulated trench isolation structure is formed by ion implanting impurities proximate to the trench edges for enhancing the oxidation rate and, hence, increasing the thickness of the oxide at the trench edges. Embodiments include ion implanting impurit... | 07/29/2003 |
| 6596642 | Material removal method for forming a structure Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the materi... | 07/22/2003 |
| 6596648 | Material removal method for forming a structure Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the materi... | 07/22/2003 |
| 6590271 | Extension of shallow trench isolation by ion implantation A shallow trench isolation (STI) structure is formed by etching trenches into the surface of a substrate in alignment with a patterned masking layer. An ion implantation of, for example, carbon, nitrogen, or oxygen, is performed so as to create an electri... | 07/08/2003 |
| 6586295 | Semiconductor device manufacturing method and semiconductor device A trench 5 for element separation is formed in a silicon substrate 1 by an etching process using an SiO2 film 2 as a mask (FIG. 1B). Side walls 18 are formed in a manner covering the trench 5 laterally (FIG. 1C). Defect-forming ions such as sil... | 07/01/2003 |
| 6583060 | Dual depth trench isolation A dual depth trench isolation structure formed between active devices and conductive well regions of same conductivity type which comprises a first inter-well isolation structure having a first isolation trench depth, a second inter-well isolation structu... | 06/24/2003 |
