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...When G.G. Hubbard learned of his future son-in-law's invention, he called it "only a toy." His daughter was engaged to a young man named Alexander Graham Bell.
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| Number | Title | Issue Date |
| 7442618 | Method to engineer etch profiles in Si substrate for advanced semiconductor devices Structures and methods for forming keyhole shaped regions for isolation and/or stressing the substrate are shown. In a first embodiment, we form an inverted keyhole shaped trench in the substrate in the first opening preferably using a two step etch. Next, we fill t... | 10/28/2008 |
| 7442620 | Methods for forming a trench isolation structure with rounded corners in a silicon substrate A process for forming STI regions comprises performing an In Situ Steam Generation (ISSG) radical conversion on a SiN liner layer within an STI trench in order to expose the top corner of the trench and simultaneously cause rounding the top corner of a liner oxide l... | 10/28/2008 |
| 7396728 | Methods of improving drive currents by employing strain inducing STI liners A method forms a semiconductor device comprising isolation structures that selectively induce strain into active regions of NMOS and PMOS devices. Form a hard mask layer over a semiconductor body. A resist layer is formed on the hard mask layer that exposes and defi... | 07/08/2008 |
| 7390717 | Trench power MOSFET fabrication using inside/outside spacers A fabrication process for a trench type power semiconductor device includes forming inside spacers over a semiconductor surface. Using the spacers as masks, trenches with gates are formed in the semiconductor body. After removing the spacers, source implants are for... | 06/24/2008 |
| 7391096 | STI structure An STI structure and fabricating method thereof are disclosed. The STI fabricating method comprises forming a pad oxide layer and a first nitride layer on a substrate. A trench is formed by etching the first nitride layer, the pad oxide layer and the substrate. An o... | 06/24/2008 |
| 7375004 | Method of making an isolation trench and resulting isolation trench A method of forming and resulting isolation region, which allows for densification of an oxide layer in the isolation region. One exemplary embodiment of the method includes the steps of forming a first trench, forming an oxide layer on the bottom and sidewalls of t... | 05/20/2008 |
| 7371655 | Method of fabricating low-power CMOS device A low-power CMOS device can be fabricated by forming a shallow trench on a silicon substrate using a gate mask and negative photoresist. This enables an extremely low profile for a junction after completion of lightly doped drain and source/drain implantations. The ... | 05/13/2008 |
| 7358588 | Trench isolation type semiconductor device which prevents a recess from being formed in a field region A trench isolation type semiconductor device in which a recess is prevented from being formed in a field region and a method of fabricating the same are provided. The trench isolation type semiconductor device includes a semiconductor substrate defined by an active ... | 04/15/2008 |
| 7339252 | Semiconductor having thick dielectric regions A method of manufacturing a semiconductor device includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The method also includes providing in the semiconductor substrate one or more trenches, first mesas and second... | 03/04/2008 |
| 7314809 | Method for forming a shallow trench isolation structure with reduced stress A method for forming a shallow trench isolation (STI) structure with reduced stress is described. An amorphous silicon layer is deposited on a trench surface of a shallow trench isolation structure, and the amorphous silicon is then oxidized by thermal oxidation to ... | 01/01/2008 |
| 7279393 | Trench isolation structure and method of manufacture therefor The present invention provides a trench isolation structure, a method for manufacturing a trench isolation structure, and a method for manufacturing an integrated circuit including the trench isolation structure. In one aspect, the method includes forming a hardmask... | 10/09/2007 |
| 7273792 | Semiconductor device and fabricating method thereof A semiconductor device including a semiconductor substrate, a device isolation region formed by filling a trench in the semiconductor substrate with dielectric material and defining device regions in the semiconductor substrate. The trench has a rounded upper edge, ... | 09/25/2007 |
| 7205207 | High performance strained CMOS devices A semiconductor device and method of manufacture provide an n-channel field effect transistor (nFET) having a shallow trench isolation with overhangs that overhang Si—SiO2 interfaces in a direction parallel to the direction of current flow and in a dire... | 04/17/2007 |
| 7163869 | Shallow trench isolation structure with converted liner layer A STI (shallow trench isolation) structure is formed with a liner layer that is converted from an initial material to a subsequent material. For example, the liner layer is initially comprised of nitride during wet etch-back of a dielectric fill material comprised o... | 01/16/2007 |
| 7160789 | Shallow trench isolation and method of forming the same A shallow trench isolation (STI) structure and a method of forming the STI structure. The STI structure defines an active region formed with a recess channel transistor. The STI structure includes a STI trench has a laterally curved rounding portion on the bottom of... | 01/09/2007 |
| 7148120 | Method of forming improved rounded corners in STI features A method for forming a shallow trench isolation (STI) structure with improved electrical isolation performance including providing a semiconductor substrate including an overlying silicon oxide layer on the semiconductor substrate and a hardmask layer on the silicon... | 12/12/2006 |
| 7141486 | Shallow trench isolation structures comprising a graded doped sacrificial silicon dioxide material and a method for forming shallow trench isolation structures A shallow trench isolation structure having a negative taper angle. A graded doped sacrificial layer is formed over a semiconductor substrate and etched to form a first trench therein having trench sidewalls that present a negative taper angle. The substrate is also... | 11/28/2006 |
| 7061075 | Shallow trench isolation using antireflection layer A film stack for forming shallow trench isolation among transistors and other devices on a semiconductor substrate is provided, including a plurality of light absorbing layers alternating between a layer of SiON and a layer of SiO2 and having a combined e... | 06/13/2006 |
| 6703315 | Method of providing a shallow trench in a deep-trench device A method of forming a shallow trench within a trench capacitor structure. This method can be used, for example, in the construction of a DRAM device. The method comprises: (1) providing a trench capacitor structure comprising (a) a silicon substrate havin... | 03/09/2004 |
| 6696348 | Wide neck shallow trench isolation region to prevent strain relaxation at shallow trench isolation region edges The present invention enables the production of improved high-speed semiconductor devices. The present invention provides the higher speed offered by strained silicon technology coupled with the smaller overall device size provided by shallow trench isola... | 02/24/2004 |
| 6693018 | Method for fabricating DRAM cell transistor having trench isolation structure The present invention relates to a method for fabricating a DRAM cell transistor having a trench isolation structure, which can prevent the reduction in effective channel length and the deterioration of a punch-through characteristic at the edge portion o... | 02/17/2004 |
| 6690080 | Semiconductor structure for isolation of semiconductor devices In an integrated circuit, particularly an integrated circuit for radio frequency applications, a semiconductor structure for isolation of semiconductor devices that includes a semiconductor substrate, at least one shallow trench extending vertically into ... | 02/10/2004 |
| 6680240 | Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide A silicon-on-insulator (SOI) device with a strained silicon film has a substrate, and a buried oxide layer on the substrate. Silicon islands are formed on the buried oxide layer, the silicon islands being separated from each other by gaps. The buried oxid... | 01/20/2004 |
| 6670275 | Method of rounding a topcorner of trench A method for pulling back SiN to increase rounding effect in a shallow trench isolation process, includes the steps of preparing a substrate of Si and forming a SiO2 layer on the substrate, forming a Si3 N4 layer on the Si... | 12/30/2003 |
| 6660599 | Semiconductor device having trench isolation layer and method for manufacturing the same A semiconductor device is formed by including the step of forming a polycrystalline silicon layer on a semiconductor substrate which includes a pad oxide. A trench is formed in the semiconductor substrate by etching sequentially a part of the polycrystall... | 12/09/2003 |
| 6653202 | Method of shallow trench isolation (STI) formation using amorphous carbon An exemplary embodiment relates to a method of shallow trench isolation (STI) formation using amorphous carbon as a sacrificial polish stop layer. The method can include polishing a silicon dioxide layer located above a wafer, polishing portions of the si... | 11/25/2003 |
| 6653200 | Trench fill process for reducing stress in shallow trench isolation The present invention provides a method of reducing stress in a shallow trench isolation region of a MOSFET device comprising the step of forming a dielectric in the shallow trench isolation region wherein the thermal expansion coefficient of the dielectr... | 11/25/2003 |
| 6653182 | Process for forming deep and shallow insulative regions of an integrated circuit Prior fabricating the transistors, a phase of forming a deep insulative trench in the substrate is followed by a phase of forming a shallow insulative trench in the substrate and extending the deep trench. The phase of forming the deep trench includes coa... | 11/25/2003 |
| 6653203 | Thin sidewall multi-step HDP deposition method to achieve completely filled high aspect ratio trenches A multi-step HDP deposition and sputtering process for void-free filling of high aspect ratio trenches and for trenches having stepped cross-sectional profiles. The method is particularly applicable to filling trenches formed in triply layered substrates ... | 11/25/2003 |
| 6649489 | Poly etching solution to improve silicon trench for low STI profile A method of etch polysilicon adjacent to a recessed STI structure feature is described. A substrate is provided with a dielectric layer thereon and a polysilicon layer on the dielectric layer. A shallow trench is formed that extends through the polysilico... | 11/18/2003 |
| 6649996 | In situ and ex situ hardmask process for STI with oxide collar application A method or process for etching a trench in an IC structure is disclosed. The IC structure might be comprised of a plurality of different component materials arranged proximate to one another, all of which need to be etched down to a target level. A first... | 11/18/2003 |
| 6645868 | Method of forming shallow trench isolation using antireflection layer Shallow trench isolation among transistors and other devices on a semiconductor substrate is provided by initially forming a layer of highly absorbing silicon rich nitride to serve as a hardmask between a semiconductor substrate and a photoresist. The hig... | 11/11/2003 |
| 6645353 | Approach to optimizing an ILD argon sputter process A sputter etch system and a method of conducting a sputter etch. The sputter etch system includes an etch chamber with a wafer pedestal having a top surface to support a wafer and a magnet configured to provide a continuous magnetic field directed at the ... | 11/11/2003 |
| 6642125 | Integrated circuits having adjacent P-type doped regions having shallow trench isolation structures without liner layers therein therebetween and methods of forming same An integrated circuit substrate includes first and second adjacent p-type doped regions spaced-apart from one another. A trench in the integrated circuit substrate is between the first and second adjacent p-type doped regions. An insulator layer in the tr... | 11/04/2003 |
| 6642536 | Hybrid silicon on insulator/bulk strained silicon technology Silicon on insulator technology and strained silicon technology provide semiconductor devices with high performance capabilities. Shallow trench isolation technology provides smaller devices with increased reliability. Bulk silicon technology provides dev... | 11/04/2003 |
| 6642557 | Isolated junction structure for a MOSFET A MOSFET structure in which the channel region is contiguous with the semiconductor substrate while the source and drain junctions are substantially isolated from the substrate, includes a dielectric volume formed adjacent and subjacent to portions of the... | 11/04/2003 |
| 6635945 | Semiconductor device having element isolation structure A semiconductor device and process of forming the device are described. The process includes forming a pad oxide film on the circuit-forming side of a semiconductor substrate; forming an oxidation prevention film on the pad oxide film; removing the oxidat... | 10/21/2003 |
| 6627506 | Thin tensile layers in shallow trench isolation and method of making same The present invention relates to a method of forming an isolation trench that comprises forming a recess in a substrate and forming a film upon the sidewall under conditions that cause the film to have a tensile load. The method includes filling the reces... | 09/30/2003 |
| 6627515 | Method of fabricating a non-floating body device with enhanced performance A method of forming a buried silicon oxide region in a semiconductor substrate with portions of the buried silicon oxide region formed underlying portions of a strained silicon shape, and where the strained silicon shape is used to accommodate a semicondu... | 09/30/2003 |
| 6627514 | Semiconductor device having a Y-shaped isolation layer and simplified method for manufacturing the Y-shaped isolation layer to prevent divot formation A semiconductor device having a Y-shaped isolation layer and a method for manufacturing the same are provided. The semiconductor device includes a Y-shaped isolation layer, which comprises side walls characterized by first and second slopes on the sides o... | 09/30/2003 |
