Class 257/E21.545 - Dielectric regions, e.g., EPIC dielectric isolation, LOCOS; trench refilling techniques, SOI technology, use of channel stoppers (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.54. This subclass
No. of patents: 252
Last issue date: 10/14/2008

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Number	Title	Issue Date
7435642	Method of evaluating the uniformity of the thickness of the polysilicon gate layer A method of evaluating the uniformity of the thickness of the polysilicon gate layer is provided. A substrate having a dense trenches area and a sparse trenches area is provided. A plurality of first trench isolation structures are formed in the sparse trenches area...	10/14/2008
7432173	Methods of fabricating silicon-on-insulator substrates having a laser-formed single crystalline film In some methods of fabricating a silicon-on-insulator substrate, a semiconductor substrate is provided that includes a single crystalline structure within at least a defined region thereof. A first insulating film is formed on the defined region of the semiconductor...	10/07/2008
7432163	Method of manufacturing semiconductor device that includes forming adjacent field regions with a separating region therebetween A method of manufacturing a semiconductor device comprises the steps of: preparing a semiconductor substrate, the semiconductor substrate having first and second predetermined regions; forming a first field region surrounding the first predetermined region; forming ...	10/07/2008
7425494	Method for forming void-free trench isolation layer Disclosed method for forming void-free isolation comprises the steps of: forming a trench in an isolation region in a semiconductor substrate; and forming a filling oxide on the semiconductor substrate to fill the trench. The filling oxide is formed by HDP-CVD proce...	09/16/2008
7402886	Memory with self-aligned trenches for narrow gap isolation regions Self-aligned trench filling is used to isolate devices in high-density integrated circuits. A deep, narrow trench isolation region is formed in a substrate between devices. The trench region includes two trench portions. A first trench portion, located above a secon...	07/22/2008
7402885	LOCOS on SOI and HOT semiconductor device and method for manufacturing One or more local oxidation of silicon (LOCOS) regions may be formed that apply compressive strain to a channel of a field-effect transistor such as a P-type field-effect transistor (PFET) or other circuit element of a semiconductor device. For instance, a pair of L...	07/22/2008
7393730	Coplanar silicon-on-insulator (SOI) regions of different crystal orientations and methods of making the same In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) providing a substrate; and (2) forming a first silicon-on-insulator (SOI) region having a first crystal orientation, a second SOI region ...	07/01/2008
7384836	Integrated circuit transistor insulating region fabrication method A transistor of an integrated circuit is provided. A first doped well region is formed in a well layer at a first active region. At least part of the first doped well region is adjacent to a gate electrode of the transistor. A recess is formed in the first doped wel...	06/10/2008
7384869	Protection of silicon from phosphoric acid using thick chemical oxide A method for protecting exposed silicon from attack by phosphoric acid during wet etching and stripping processes is provided. According to various embodiments of the method, a thick chemical oxide layer can be formed on the exposed silicon to protect the exposed po...	06/10/2008
7385275	Shallow trench isolation method for shielding trapped charge in a semiconductor device A semiconductor structure and associated method for forming the semiconductor structure. The semiconductor structure comprises a first field effect transistor (FET), a second FET, and a shallow trench isolation (STI) structure. The first FET comprises a channel regi...	06/10/2008
7358145	Method of fabricating shallow trench isolation structure A method of fabricating a shallow trench isolation structure is provided. A substrate is provided with a pad layer, a mask layer and a shallow trench formed therein. A liner oxide layer is formed on the sidewall of the shallow trench and then a silicon nitride layer...	04/15/2008
7348639	Method for providing a deep connection to substrate or buried layer in a semiconductor device A system and method is disclosed for providing a deep connection to a substrate or buried layer of a semiconductor device. Three shallow trenches are etched halfway through a layer of epitaxial silicon that is located on a substrate. A second doped layer is created ...	03/25/2008
7348254	Method of fabricating fin field-effect transistors A method of fabricating a fin field-effect transistor that may enable a reduction in the number of process steps, by forming the fin structure by etching away a predetermined thickness of an element isolation layer. The method includes steps of sequentially forming ...	03/25/2008
7344954	Method of manufacturing a capacitor deep trench and of etching a deep trench opening A substrate is provided having an oxide layer, a first nitride-silicon, a STI, and a second nitride-silicon. A pattern poly-silicon layer on the second nitride-silicon layer is etched to form a deep trench opening. Etching the pattern poly-silicon layer also deepens...	03/18/2008
7342272	Flash memory with recessed floating gate A flash memory device where the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device density. The floating gate can also be elevated above the substr...	03/11/2008
7335568	Method of forming doped regions in the bulk substrate of an SOI substrate to control the operational characteristics of transistors formed thereabove, and an integrated circuit device comprising same In one illustrative embodiment, the method comprises providing an SOI substrate comprised of an active layer, a buried insulation layer and a bulk substrate, forming a doped region in the bulk substrate under the active layer, forming a plurality of transistors abov...	02/26/2008
7327009	Selective nitride liner formation for shallow trench isolation A method for forming a divot free nitride lined shallow trench isolation (STI) feature including providing a substrate including an STI trench extending through an uppermost hardmask layer into a thickness of the substrate exposing the substrate portions; selectivel...	02/05/2008
7326625	Trench structure having a void and inductor including the trench structure In a method of forming a trench structure having a wide void therein, a first trench having a first width and a first depth is formed in a substrate. The first trench is filled with a first insulation layer pattern defining the void in the first trench. A second tre...	02/05/2008
7327014	Semiconductor integrated circuit device and process for manufacturing the same A large area dummy pattern DL is formed in a layer underneath a target T2 region formed in a scribe region SR of a wafer. A small area dummy pattern in a lower layer and a small area dummy pattern Ds2 in an upper layer are disposed in a region where th...	02/05/2008
7323739	Semiconductor device having recess and planarized layers A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a silicon substrate having an electrically isolated active area. A gate oxide, as well as other components of a ...	01/29/2008
7307002	Non-critical complementary masking method for poly-1 definition in flash memory device fabrication A method is disclosed for the definition of the poly-1 layer in a semiconductor wafer. A non-critical mask is used to recess field oxides in the periphery prior to poly-1 deposition by an amount equal to the final poly-1 thickness. A complimentary non-critical mask ...	12/11/2007
7303964	Self-aligned STI SONOS Methods 300 and 350 are disclosed for fabricating shallow isolation trenches and structures in multi-bit SONOS flash memory devices. One method aspect 300 comprises forming 310 a multi-layer dielectric-charge trapping-dielectric stack ...	12/04/2007
7297608	Method for controlling properties of conformal silica nanolaminates formed by rapid vapor deposition A method employing atomic layer deposition rapid vapor deposition (RVD) conformally deposits a dielectric material on small features of a substrate surface. The resulting dielectric film is then annealed using a high density plasma (HDP) at a temperature under 500°...	11/20/2007
7294573	Method for controlling poly 1 thickness and uniformity in a memory array fabrication process According to one exemplary embodiment, a method includes planarizing a layer of polysilicon situated over field oxide regions on a substrate to form polysilicon segments, where the polysilicon segments have top surfaces that are substantially planar with top surface...	11/13/2007
7294556	Method of forming trench isolation in the fabrication of integrated circuitry This invention includes methods of forming a phosphorus doped silicon dioxide comprising layers, and methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of forming a phosphorus doped silicon dioxide compris...	11/13/2007
7288452	Method for manufacturing semiconductor device A method of manufacturing a semiconductor device including forming an ONO film on a semiconductor substrate and a hard mask layer on the ONO film, forming a trench by etching the hard mask layer and the ONO film on a field region of the semiconductor substrate using...	10/30/2007
7279396	Methods of forming trench isolation regions with nitride liner The invention includes methods of forming trench isolation regions. In one implementation, a masking material is formed over a semiconductor substrate. The masking material comprises at least one of tungsten, titanium nitride and amorphous carbon. An opening is form...	10/09/2007
7273793	Methods of filling gaps using high density plasma chemical vapor deposition The invention includes a method of filling gaps in a semiconductor substrate. A substrate and a gas mixture containing at least one heavy-hydrogen compound are provided within a reaction chamber. The gas mixture is reacted to form a layer of material over the substr...	09/25/2007
7268043	Semiconductor device and method of manufacturing the same A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gat...	09/11/2007
7265017	Method for manufacturing partial SOI substrates There is closed a semiconductor device which comprises a semiconductor substrate including an SOI region where a first insulating film is buried, and a non-SOI region, the semiconductor substrate being provided with a boundary region formed between the SOI region an...	09/04/2007
7265420	Semiconductor substrate layer configured for inducement of compressive or expansive force An integrated circuit (IC) utilizes a strained layer. The substrate can utilize trenches in a base layer to induce stress in a layer. The trenches define pillars on a back side of a bulk substrate or base layer of a semiconductor-on-insulator (SOI) wafer. ...	09/04/2007
7262111	Method for providing a deep connection to a substrate or buried layer in a semiconductor device A system and method is disclosed for providing a deep connection to a substrate or buried layer of a semiconductor device. Three shallow trenches are etched halfway through a layer of epitaxial silicon that is located on a substrate. A second doped layer is created ...	08/28/2007
7259069	Semiconductor device and method of manufacturing the same A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gat...	08/21/2007
7259073	Semiconductor device and method of manufacturing the same A method of manufacturing a semiconductor device that suppresses emergence of a waste in an isolation trench formation process is to be provided. The method comprises forming an isolation trench having a predetermined depth from a surface of a semiconductor s...	08/21/2007
7244658	Low stress STI films and methods The present invention generally relates to low compressive stress doped silicate glass films for STI applications. By way of non-limited example, the stress-lowering dopant may be a fluorine dopant, a germanium dopant, or a phosphorous dopant. The low compressive st...	07/17/2007
7244991	Semiconductor integrated device A semiconductor integrated apparatus, including: an SOI (Silicon On Insulator) substrate which has a support substrate and an embedded insulation film; an NMOSFET, a PMOSFET and an FBC (Floating Body Cell) formed on the SOI substrate separately from each other; a p ...	07/17/2007
7235460	Method of forming active and isolation areas with split active patterning A process for forming isolation and active regions, wherein the patterning of an oxidation-barrier active stack is performed separately in the PMOS and NMOS regions. After the active stack is in place, two masking steps are used: one exposes the isolation areas on t...	06/26/2007
7224035	Apparatus and fabrication methods for incorporating sub-millimeter, high-resistivity mechanical components with low-resistivity conductors while maintaining electrical isolation therebetween Fabricating electrical isolation properties into a MEMS device is described. One embodiment comprises a main substrate layer of a high-resistivity semiconductor material, such as high-resistivity silicon. The high-resistivity substrate is then controllably doped to ...	05/29/2007
7221035	Semiconductor structure avoiding poly stringer formation The present invention discloses a semiconductor structure avoiding the poly stringer formation in semiconductor processing. A semiconductor device is divided into a memory cell area and a peripheral portion. A plurality of parallel first isolation devices are positi...	05/22/2007
7211497	Method for fabricating semiconductor devices According to the present invention, an oxide film with the film quality almost equivalent to that of the thermal oxide can be formed by the low-temperature treatment. After removing an insulator on the active region of the substrate which constitutes a semiconductor...	05/01/2007

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Class 257/E21.545 - Dielectric regions, e.g., EPIC dielectric isolation, LOCOS; trench refilling techniques, SOI technology, use of channel stoppers (EPO)