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| Number | Title | Issue Date |
| 7442609 | Method of manufacturing a transistor and a method of forming a memory device with isolation trenches A method of manufacturing a transistor. In one embodiment, the method includes forming a gate electrode by defining a gate groove in the substrate. A plate-like portion is defined in each of the trenches at a position adjacent to the groove so that the two plate-lik... | 10/28/2008 |
| 7429518 | Method for forming shallow trench isolation of semiconductor device A shallow trench isolation well is formed to be very thin in a highly integrated semiconductor device. When critical dimension (CD) is small, it is difficult to reduce the width of the photosensitive layer pattern for forming a trench to no more than a predetermined... | 09/30/2008 |
| 7402885 | LOCOS on SOI and HOT semiconductor device and method for manufacturing One or more local oxidation of silicon (LOCOS) regions may be formed that apply compressive strain to a channel of a field-effect transistor such as a P-type field-effect transistor (PFET) or other circuit element of a semiconductor device. For instance, a pair of L... | 07/22/2008 |
| 7320926 | Shallow trench filled with two or more dielectrics for isolation and coupling for stress control A method for forming shallow trenches having different trench fill materials is described. A stop layer is provided on a substrate. A plurality of trenches is etched through the stop layer and into the substrate. A first layer is deposited over the stop layer and fi... | 01/22/2008 |
| 7312122 | Self-aligned element isolation film structure in a flash cell and forming method thereof A self-aligned element isolation film structure in a flash memory cell and a forming method thereof are disclosed. An example method of forming a self-aligned element isolation film structure in a flash memory cell forms an insulating layer on a semiconductor substr... | 12/25/2007 |
| 7307324 | MOS transistor in an active region After an isolation region is formed using a field-forming silicon nitride film, this silicon nitride film is patterned, thereby a gate trench is formed. Next, a gate electrode material is buried into the gate trench, and this is etched back. Thereafter, the silicon ... | 12/11/2007 |
| 7297608 | Method for controlling properties of conformal silica nanolaminates formed by rapid vapor deposition A method employing atomic layer deposition rapid vapor deposition (RVD) conformally deposits a dielectric material on small features of a substrate surface. The resulting dielectric film is then annealed using a high density plasma (HDP) at a temperature under 500°... | 11/20/2007 |
| 7294573 | Method for controlling poly 1 thickness and uniformity in a memory array fabrication process According to one exemplary embodiment, a method includes planarizing a layer of polysilicon situated over field oxide regions on a substrate to form polysilicon segments, where the polysilicon segments have top surfaces that are substantially planar with top surface... | 11/13/2007 |
| 7279397 | Shallow trench isolation method A method (200) of forming an isolation structure is presented, in which a hard mask layer (304, 308) is formed (204, 206) over the isolation and active regions (305, 303) of a semiconductor body (306), and a dopant is selectively p... | 10/09/2007 |
| 7268058 | Tri-gate transistors and methods to fabricate same Embodiments of the invention provide a method for effecting uniform silicon body height for silicon-on-insulator transistor fabrication. For one embodiment, a sacrificial oxide layer is disposed upon a semiconductor substrate. The oxide layer is etched to form a tre... | 09/11/2007 |
| 7253064 | Cascode I/O driver with improved ESD operation A cascode I/O driver is described that includes a barrier formed in the shared region between the two transistors. The barrier region allows the I/O driver to be designed to primarily meet I/O requirements. Accordingly, improved operating speeds are achieved. An sys... | 08/07/2007 |
| 7208812 | Semiconductor device having STI without divot and its manufacture The method of manufacturing a semiconductor device has the steps of: etching a semiconductor substrate to form an isolation trench by using as a mask a pattern including a first silicon nitride film and having a window; depositing a second silicon nitride film cover... | 04/24/2007 |
| 7205242 | Method for forming isolation layer in semiconductor device The present invention relates to a method for forming an insulating layer in a semiconductor device. After a first oxide film is formed in a trench, an impurity remaining on the first oxide film in the process of etching the first oxide film using a gas containing f... | 04/17/2007 |
| 7196396 | Semiconductor device having STI without divot and its manufacture The method of manufacturing a semiconductor device has the steps of: etching a semiconductor substrate to form an isolation trench by using as a mask a pattern including a first silicon nitride film and having a window; depositing a second silicon nitride film cover... | 03/27/2007 |
| 7141496 | Method of treating microelectronic substrates A method of treating a dielectric surface portion of a semiconductor substrate, comprising the steps of: (a) providing a semiconductor substrate having a dielectric surface portion; and then (b) treating said dielectric surface portion with a coating reagent, the co... | 11/28/2006 |
| 7135371 | Methods of fabricating semiconductor devices Methods of fabricating semiconductor devices are disclosed. One example method includes forming a gate oxide and a gate electrode on a semiconductor substrate; performing a first ion implantation process for the formation of an LDD (lightly doped drain) region in th... | 11/14/2006 |
| 7132333 | Transistor, memory cell array and method of manufacturing a transistor A transistor, memory cell array and method of manufacturing a transistor are disclosed. In one embodiment, the invention refers to a transistor, which is formed at least partially in a semiconductor substrate, comprising a first and a second source/drain regions, a ... | 11/07/2006 |
| 7118988 | Vertically wired integrated circuit and method of fabrication A static random access memory (SRAM) cell structure is created in a three-dimensional format as a vertical stack of wired transistors. These transistors are fabricated from crystalline silicon, and supplemental wiring structure features are fabricated to comprise a ... | 10/10/2006 |
| 7112513 | Sub-micron space liner and densification process A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an oxygen barrier is deposited into the trench. An expandable, oxidizable liner, preferably amorphous silicon,... | 09/26/2006 |
| 6656803 | Radiation hardened semiconductor memory A radiation hardened memory device having static random access memory cells includes active gate isolation structures to prevent leakage currents between active regions formed adjacent to each other on a substrate. The active gate isolation structure incl... | 12/02/2003 |
| 6642559 | Structure and process for improving high frequency isolation in semiconductor substrates An isolation structure for high frequency integrated circuits is a conductive material disposed over a region of active gallium arsenide substrate. The conductive material over the active region creates a lossy RF path to reduce undesired coupling between... | 11/04/2003 |
| 6548847 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING A FIRST WIRING STRIP EXPOSED THROUGH A CONNECTING HOLE, A TRANSITION-METAL FILM IN THE CONNECTING HOLE AND AN ALUMINUM WIRING STRIP THEREOVER, AND A TRANSITION-METAL NITRIDE FILM BETWEEN THE ALUMINUM WIRING STRIP AND THE TRANSITION-METAL FILM Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating fi... | 04/15/2003 |
| 6344116 | Monocrystalline three-dimensional integrated-circuit technology Three technologies realize monocrystalline three-dimensional (3-D) integrated circuits: (1) silicon sputter epitaxy permitting fast growth at low temperature; (2) real-time pattern generation using a pixel-by-pixel programmable device to create a patterne... | 02/05/2002 |
| 6342412 | Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating fi... | 01/29/2002 |
| 6287881 | Semiconductor device with low parasitic capacitance A method of fabricating a semiconductor device having active components grown on a substrate, involves providing a semiconductor substrate on which the active components are grown, and doping the semiconductor substrate to render it non conductive and the... | 09/11/2001 |
| 6103590 | SiC patterning of porous silicon A method of selectively forming porous silicon regions (106) in a silicon substrate (100). A masking layer (104) of SiC is deposited by PECVD over the substrate (100) using an organosilicon precursor gas such as trimethylsilane, silane/methane, or tetrame... | 08/15/2000 |
| 6046109 | Creation of local semi-insulating regions on semiconductor substrates The present invention solves the problem of how to form local regions of semi-insulating material within a single crystal substrate. It does this by irradiating the semiconductor with a high energy beam capable of producing radiation damage along its path... | 04/04/2000 |
| 6037629 | Trench transistor and isolation trench An IGFET with a gate electrode in a transistor trench adjacent to an isolation trench is disclosed. The trenches are formed in a semiconductor substrate. A gate insulator is on a bottom surface of the transistor trench, insulative spacers are adjacent to ... | 03/14/2000 |
| 5937318 | Monocrystalline three-dimensional integrated circuit A monocrystalline monolith contains a 3-D array of interconnected lattice-matched devices (which may be of one kind exclusively, or that kind in combination with one or more other kinds) performing digital, analog, image-processing, or neural-network func... | 08/10/1999 |
| 5923073 | Method of manufacturing a semiconductor device and semiconductor device manufactured according to the method A manufacturing method of semiconductor devices and semiconductor devices isolated by a trench portion. The trench portion is refilled with a Si epitaxial growth layer. The trench has a first insulating layer on its side wall and a second insulating layer... | 07/13/1999 |
| 5872415 | Microelectronic structures including semiconductor islands A microelectronic structure includes a substrate, a semiconductor island on the substrate, and a filler material on the substrate and surrounding the semiconductor island. The semiconductor island includes a first semiconductor material and has a planar i... | 02/16/1999 |
| 5849614 | Method of isolation by active transistors with grounded gates An isolation gate structure is formed between active areas on a P-type semiconductor substrate. The isolation structure includes a thick gate oxide layer over which is formed a P-doped polycrystalline silicon layer. The polycrystalline silicon layer is el... | 12/15/1998 |
| 5840589 | Method for fabricating monolithic and monocrystalline all-semiconductor three-dimensional integrated circuits A method is described for growing a single crystal having three-dimensional (3-D) doping patterns created within it during growth while maintaining a plane growth surface, creating junction-isolated devices and interconnections, forming a 3-D integrated c... | 11/24/1998 |
| 5821629 | Buried structure SRAM cell and methods for fabrication An improved SRAM cell having ultra-high density and methods for fabrication are described. Each SRAM cell, according to the present invention, has its own buried structure, including word lines (i.e., gate regions) and bit lines (i.e., source/drain region... | 10/13/1998 |
| 5786604 | Element-isolated hydrogen-terminated diamond semiconductor device and its manufacturing method A diamond semiconductor device having at least one MESFET integrated on a single diamond substrate and insulated from other semiconductor elements is made by preparing a homoepitaxial diamond film 1 having a hydrogen-terminated surface; then making a drai... | 07/28/1998 |
| 5780340 | Method of forming trench transistor and isolation trench An IGFET with a gate electrode in a transistor trench adjacent to an isolation trench is disclosed. The trenches are formed in a semiconductor substrate. A gate insulator is on a bottom surface of the transistor trench, insulative spacers are adjacent to ... | 07/14/1998 |
| 5780882 | Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating fi... | 07/14/1998 |
| 5739589 | Semiconductor integrated circuit device process for fabricating the same and apparatus for fabricating the same Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating fi... | 04/14/1998 |
| 5700712 | Method for manufacturing an insulating trench in an SOI substrate for smartpower technologies A method for producing an insulating trench in an SOI substrate having integrated logic elements and high-voltage power components is provided. A trench extending down to an insulating layer is etched and covered with a doped silicon structure. Diffusion ... | 12/23/1997 |
| 5602049 | Method of fabricating a buried structure SRAM cell An improved SRAM cell having ultra-high density and methods for fabrication are described. Each SRAM cell, according to the present invention, has its own buried structure, including word lines (i.e., gate regions) and bit lines (i.e., source/drain region... | 02/11/1997 |
