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| Number | Title | Issue Date |
| 7442602 | Methods of fabricating phase change memory cells having a cell diode and a bottom electrode self-aligned with each other Integrated circuit devices are provided having a vertical diode therein. The devices include an integrated circuit substrate and an insulating layer on the integrated circuit substrate. A contact hole penetrates the insulating layer. A vertical diode is in a lower r... | 10/28/2008 |
| 7315083 | Circuit device and manufacturing method thereof A circuit device suitable for connecting a plurality of laminated wiring layers to each other through an insulating layer, and a manufacturing method thereof are provided. According to a hybrid integrated circuit device of the present invention and a manufacturing m... | 01/01/2008 |
| 7294561 | Internal gettering in SIMOX SOI silicon substrates The present invention provides methods for forming SOI wafers having internal gettering layers for sequestering metallic impurities. More particularly, in one embodiment of the invention, a plurality of sites for sequestering metallic impurities are formed in a sili... | 11/13/2007 |
| 7262122 | Method of forming metal line in semiconductor memory device The present invention relates to a method of forming a metal line of a semiconductor memory device. According to the present invention, after a drain contact plug formed within an interlayer insulating film protrudes, a nitride film is formed on the top of the drain... | 08/28/2007 |
| 7223694 | Method for improving selectivity of electroless metal deposition A method of depositing a metal cladding on conductors in a damascene process is described. The potential between, for instance, cobalt ions in electroless solution and the surface of an ILD between the conductors is adjusted so as to repel the metal from the ILD. | 05/29/2007 |
| 7205219 | Methods of forming integrated circuits devices having pad contact plugs in the cell array and peripheral circuit regions of the integrated circuit substrate Integrated circuit devices, for example, dynamic random access memory (DRAM) devices, are provided including an integrated circuit substrate having a cell array region and a peripheral circuit region. A buried contact plug is provided on the integrated circuit subst... | 04/17/2007 |
| 7180152 | Process for resurf diffusion for high voltage MOSFET A starting wafer for high voltage semiconductor devices is formed by implanting arsenic into the top surface of a p type silicon substrate wafer to a depth of about 0.1 micron. A N type non-graded epitaxial layer is then grown atop the substrate without any diffusio... | 02/20/2007 |
| 7161198 | Semiconductor integrated circuit device having MOS transistor An N-channel MOS transistor of a semiconductor device having a high withstand voltage employs a drain structure with a low concentration and a large diffusion depth, which causes a problem in that a sufficiently high withstand voltage cannot be obtained due to a par... | 01/09/2007 |
| 7144829 | Method for fabricating semiconductor device and semiconductor substrate A first thermal treatment, which is performed at a temperature within 650–750° C. for 30–240 minutes, and thereafter a second thermal treatment, which is performed at a temperature within 900–1100° C. for 30–120 minutes, are performed as the initial therma... | 12/05/2006 |
| 6624497 | Semiconductor device with a reduced mask count buried layer An N type buried layer is formed, in one embodiment, by a non selective implant on the surface of a wafer and later diffusion. Subsequently, the wafer is masked and a selective P type buried layer is formed by implant and diffusion. The coefficient of dif... | 09/23/2003 |
| 6600200 | MOS transistor, method for fabricating a MOS transistor and method for fabricating two complementary MOS transistors A MOS transistor and a method for fabricating the same include producing a well doped by a first conductivity type in a semiconductor substrate. An epitaxial layer having a dopant concentration of less than 1017 cm-3 is disposed on a... | 07/29/2003 |
| 6589336 | Production method for silicon epitaxial wafer and silicon epitaxial wafer Performing the post-implantation annealing for recovering crystallinity in a hydrogen atmosphere can successfully suppress the surface roughening on the ion-implanted layers without pre-implantation oxidation. This allows omission of the pre-implantation ... | 07/08/2003 |
| 6500723 | Method for forming a well under isolation and structure thereof A number of small wells under the isolation layer are formed using the same mask made of photoresist and implant step that is used for the regular wells. The small wells are formed close enough together so that they merge during normal subsequent semicond... | 12/31/2002 |
| 6465844 | Power semiconductor device and method of manufacturing the same A power semiconductor device has a plurality of U-shaped buried layers buried in a drift layer and made of either an insulating material or a semiconductor having a wider bandgap than that of the semiconductor of the drift layer. The ratio of the product ... | 10/15/2002 |
| 6461920 | Semiconductor device and method of manufacturing the same In a semiconductor device, a plurality of MIS transistors of the same conductivity type having different thresholds are formed at a main surface of semiconductor substrate, and impurity profiles on section extending in a depth direction from the main surf... | 10/08/2002 |
| 6444551 | N-type buried layer drive-in recipe to reduce pits over buried antimony layer A method of driving-in antimony into a wafer, including the following steps. A wafer is loaded into an annealing furnace/tool. The wafer having an area of implanted antimony ions. The wafer is annealed a first time at a first temperature in the presence o... | 09/03/2002 |
| 6410409 | Implanted barrier layer for retarding upward diffusion of substrate dopant Boron forming a deep P+ layer within a semiconductor substrate upwardly diffuses during subsequent heat treatment operations such as annealing. A method for retarding this upward diffusion of boron includes implanting nitrogen to form a nitrogen barrier l... | 06/25/2002 |
| 6362075 | Method for making a diffused back-side layer on a bonded-wafer with a thick bond oxide Integrated circuits, semiconductor devices and methods for making the same are described. Each embodiment shows a diffused, doped backside layer in a device wafer that is oxide bonded to a handle wafer. The diffused layer may originate in the device wafer... | 03/26/2002 |
| 6346460 | Low cost silicon substrate with impurity gettering and latch up protection and method of manufacture A low cost method of manufacturing a silicon substrate having both impurity gettering and protection against CMOS latch up. The method includes performing a low energy implant of a selected acceptor ion to form a low resistivity buried layer closely adjac... | 02/12/2002 |
| 6344116 | Monocrystalline three-dimensional integrated-circuit technology Three technologies realize monocrystalline three-dimensional (3-D) integrated circuits: (1) silicon sputter epitaxy permitting fast growth at low temperature; (2) real-time pattern generation using a pixel-by-pixel programmable device to create a patterne... | 02/05/2002 |
| 6316817 | MeV implantation to form vertically modulated N+ buried layer in an NPN bipolar transistor High energy implantation through varying vertical thicknesses of one or more films is used to form a vertically modulated sub-collector, which simultaneously reduces both the vertical and lateral components of parasitic collector resistance in a verticall... | 11/13/2001 |
| 6312981 | Method for manufacturing semiconductor device A method for producing a semiconductor device includes the steps of: forming an impurity diffusion layer for controlling a threshold voltage by ion implantation; and conducting a high-temperature rapid heat treatment for recovering crystal defects generat... | 11/06/2001 |
| 6297120 | Method of manufacturing a semiconductor device To provide a method of manufacturing a semiconductor device in which an epitaxial growth film is formed on a semiconductor substrate having a buried layer, which is capable of reducing the manufacturing time of the semiconductor device or reducing the IC ... | 10/02/2001 |
| 6281565 | Semiconductor device and method for producing the same A semiconductor device comprising an isolating layer (diffusion layer) having a deep depth which can be produced with improved productivity and a method of the same. The semiconductor device comprises a semiconductor substrate of a first conductivity type... | 08/28/2001 |
| 6262457 | Method of producing a transistor structure Additional degrees of freedom are provided for optimizing the component properties by combining two doping profiles. The threshold voltage of NMOS or DMOS transistors can be set through the process parameters involved in the introduction and outward diffu... | 07/17/2001 |
| 6251718 | Method for manufacturing semiconductor device A method for producing a semiconductor device includes the steps of: forming an impurity diffusion layer for controlling a threshold voltage by ion implantation; and conducting a high-temperature rapid heat treatment for recovering crystal defects generat... | 06/26/2001 |
| 6180986 | Semiconductor device and method of manufacturing the same First and second regions of different thicknesses are provided on a p- epitaxial layer formed on the main surface of a p+ silicon substrate. A p-well is formed in the first region having a relatively small thickness, and an n-well is... | 01/30/2001 |
| 6144079 | Semiconductor device and method of manufacturing the same In a semiconductor device, a plurality of MIS transistors of the same conductivity type having different thresholds are formed at a main surface of semiconductor substrate, and impurity profiles on section extending in a depth direction from the main surf... | 11/07/2000 |
| 6114729 | Plural wells structure in a semiconductor device Wells of a semiconductor device suitable for achieving high integration, and a method for forming the same are disclosed. The wells of a semiconductor device include a first conductivity type semiconductor substrate where a cell region and a periphery reg... | 09/05/2000 |
| 6097046 | Vertical field effect transistor and diode A vertical field effect transistor (1400) and diode (1450) formed on a single III-V substrate. The diode cathode and the transistor drain or collector may be formed in a common layer (1408).... | 08/01/2000 |
| 6066522 | Semiconductor device and method for producing the same A semiconductor device include: a substrate of a conductivity type; a first well provided in the substrate and of the same conductivity type as the conductivity type of the substrate; a second well provided in the substrate and of an opposite conductivity... | 05/23/2000 |
| 6037632 | Semiconductor device A semiconductor device is disclosed, which comprises a first main electrode, a second main electrode, a high-resistance semiconductor layer of first conductivity type interposed between the first main electrode and the second main electrode, and at least ... | 03/14/2000 |
| 6001711 | Process of fabricating semiconductor device having gettering site layer between insulating layer and active semiconductor layer Phosphorous ion is implanted into an SOI substrate under the conditions that the concentration is maximized in the upper silicon layer of the SOI substrate so as to forming a heavily-doped damaged layer, and the heavily-doped damaged layer is partially cu... | 12/14/1999 |
| 5981327 | Method for forming wells of semiconductor device A method for forming wells of a semiconductor device, comprising the steps of forming a plurality of field insulating layers on a field region of a semiconductor substrate; forming first impurity regions of a first conductive type at a first depth beneath... | 11/09/1999 |
| 5958505 | Layered structure with a silicide layer and process for producing such a layered structure A process for producing a layered structure in which a silicide layer on a silicon substrate is subjected to local oxidation to cause the boundary layer side of the silicide layer to grow into the silicon substrate.... | 09/28/1999 |
| 5952720 | Buried contact structure A buried contact structure is provided for forming a contact between a source/drain region of a MOSFET and polysilicon conducting line. The polysilicon conducting line is formed on a field oxide region and extends onto the surface of the semiconductor sub... | 09/14/1999 |
| 5943595 | Method for manufacturing a semiconductor device having a triple-well structure A method of manufacturing a semiconductor device having a triple-well structure, includes the steps of: forming a first well layer of a second conductivity type by implanting, as a first ion implantation, impurity ions of the second conductivity type to a... | 08/24/1999 |
| 5937318 | Monocrystalline three-dimensional integrated circuit A monocrystalline monolith contains a 3-D array of interconnected lattice-matched devices (which may be of one kind exclusively, or that kind in combination with one or more other kinds) performing digital, analog, image-processing, or neural-network func... | 08/10/1999 |
| 5898007 | Method for forming wells of a semiconductor device A method for forming wells of a semiconductor device which involves the formation of an additional ion implanted layer and a double rapid thermal annealing for a short period of time, thereby completely removing defects while maintaining a constant resist... | 04/27/1999 |
| 5895251 | Method for forming a triple-well in a semiconductor device A method of forming a triple-well in a semiconductor device, includes the steps of forming a second conductivity type impurity region in a first conductivity type semiconductor substrate, forming an epitaxial layer on the semiconductor substrate, forming ... | 04/20/1999 |
