Class 257/E21.524 - Circuit for characterizing or monitoring manufacturing process, e.g., whole test die, wafer filled with test structures, onboard devices incorporated on each die, process/product control monitors or PCM, devices in scribe-line/kerf, drop-in devices (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.522. This subclass
No. of patents: 23
Last issue date: 09/16/2008

Number	Title	Issue Date
7425458	Selectable decoupling capacitors for integrated circuits and associated methods Selectable capacitors are used to modify performance characteristics of functional circuit elements of an integrated circuit (IC). In an embodiment, the decoupling capacitors are implemented as additional or alternative mounting pads on a surface of the IC. At least...	09/16/2008
7423288	Technique for evaluating a fabrication of a die and wafer The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performa...	09/09/2008
7407822	Method for inspecting insulating film for film carrier tape for mounting electronic components thereon, inspection apparatus for inspecting the insulating film, punching apparatus for punching the insulating film, and method for controlling the punching apparatus The invention provides an inspection apparatus and an inspection method for detecting defects, a punching apparatus, and a method for controlling a punching apparatus, for the purpose of immediate detection of debris from being lifted toward the surface of an insula...	08/05/2008
7390682	Method for testing metal-insulator-metal capacitor structures under high temperature at wafer level A test methodology is provided for testing metal-insulator-metal (MIM) capacitor structures under high temperatures at the wafer level. A resistor is formed on a region of dielectric isolation material formed in a semiconductor substrate. The MIM capacitor is formed...	06/24/2008
7372072	Semiconductor wafer with test structure The invention relates to a semiconductor wafer (1) having a plurality of first sawing regions (201-211) running parallel to one another in a first direction (X) and a plurality of second sawing regions (301-311) running parallel to...	05/13/2008
7355201	Test structure for measuring electrical and dimensional characteristics A test structure includes first and second combs, at least a first pair of base nodes, and a second pair of finger nodes. The first comb includes a first base and a first plurality of fingers extending from the first base. The second comb includes a second base and ...	04/08/2008
7342295	Porogen material A porogen material for forming a dielectric porous film. The porogen material may include a silicon based dielectric precursor and a silicon containing porogen. The porous film may have a substantially uniform dielectric constant value throughout. Methods of forming...	03/11/2008
7323357	Method for manufacturing a resistively switching memory cell and memory device based thereon The invention relates to a method for manufacturing at least one phase change memory cell. The method at least fabricating at least one first lamellar spacer of conductive material, which is electrically coupled to the PCM material of the memory cell; fabricating at...	01/29/2008
7317203	Method and monitor structure for detecting and locating IC wiring defects A 3-dimensional PCM structure and method for using the same for carrying out 3-dimensional integrated circuit wiring electrical testing and failure analysis in an integrated circuit manufacturing process, the method including forming a first metallization layer; car...	01/08/2008
7288848	Overlay mark for measuring and correcting alignment errors An overlay mark includes at least one hole array formed on a semiconductor substrate and at least one linear trench adjacent to the hole array. The hole array may be formed adjacent to the linear trench along a predetermined direction. When alignment errors among pa...	10/30/2007
7282378	Method of manufacturing inspection unit A conductive member having a first face adapted to be mounted on a board on which an inspection circuit is arranged, and a second face adapted to be opposed to a device to be inspected is prepared. The conductive member is formed with a first through hole having a f...	10/16/2007
7253436	Resistance defect assessment device, resistance defect assessment method, and method for manufacturing resistance defect assessment device A resistance defect assessment device provided on a wafer for assessing a resistance variation defect in a component of an integrated circuit device, the resistance defect assessment device including test patterns capable of measuring a resistance variation componen...	08/07/2007
7224042	Integrated circuit wafer with inter-die metal interconnect lines traversing scribe-line boundaries A metal interconnect structure formed over a substrate in an integrated circuit that traverses a scribe-line boundary between a first die and a second die includes at least one metal interconnect line that traverses the scribe-line boundary. A switch is coupled betw...	05/29/2007
7186280	Method of inspecting a leakage current characteristic of a dielectric layer and apparatus for performing the method A method of inspecting a leakage current of a dielectric layer on a substrate including a cell array region having a plurality of cell blocks including a patterned structure, the dielectric layer formed on the patterned structure, and a peripheral circuit region inc...	03/06/2007
7170189	Semiconductor wafer and testing method therefor Circuits under electrode terminals and a nonconductor layer of the electrode terminals in semiconductor devices are prevented from being damaged during a test, such as a burn-in test, on the semiconductor devices formed on a wafer. Alignment patterns provided on the...	01/30/2007
7170090	Method and structure for testing metal-insulator-metal capacitor structures under high temperature at wafer level A test structure and a test methodology are provided for testing metal-insulator-metal (MIM) capacitor structures under high temperatures at the wafer level. The test structure includes a resistor formed on a region of dielectric isolation material formed in a semic...	01/30/2007
7163829	Method of integration testing for packaged electronic components A method of integration testing for packaged electronic components is capable of improving a conventional testing for packaged electronic components. In this method, non-tested sides of the packaged electronic components are stuck with a downward exposure onto a tes...	01/16/2007
7161175	Inter-dice signal transfer methods for integrated circuits The present invention discloses novel methods to transfer data between a plurality of integrated circuit dice on a semiconductor wafer. Each individual die contains internal circuits to control data transfer to nearby dice. Wafer level data transfer is achieved by a...	01/09/2007
7132303	Stacked semiconductor device assembly and method for forming One embodiment relates to using a robust metal layer of a semiconductor device to form landing pads. In one embodiment, a sputterable, nonwettable refractory metal is used as a solder mask for the landing pads. A second device may then be coupled to the robust metal...	11/07/2006
7105379	Implementation of protection layer for bond pad protection A method of protecting a bond pad during die-sawing comprising the following steps. A substrate having a bond pad formed thereover is provided. A bond pad protection layer is formed over the bond pad. The substrate is die-sawed and the bond pad protection layer is r...	09/12/2006
7098053	Method of producing semiconductor elements using a test structure Testing the production of semiconductor elements on a substrate, the semiconductor elements having a plurality of cell types, by providing at least one test structure on the substrate with a number of test cells having cell types similar to one or more of the plural...	08/29/2006
7067842	Method and apparatus for monitoring parasitic inductance The present invention includes a method and apparatus for measuring a parasitic inductance associated with a portion of an integrated circuit fabricated on a semiconductor substrate. A test chip for measuring the parasitic inductance is fabricated together with the ...	06/27/2006
6831294	Semiconductor integrated circuit device having bump electrodes for signal or power only, and testing pads that are not coupled to bump electrodes In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for p...	12/14/2004

PatentStorm

Bizarre Patents

PatentStorm News

Class 257/E21.524 - Circuit for characterizing or monitoring manufacturing process, e.g., whole test die, wafer filled with test structures, onboard devices incorporated on each die, process/product control monitors or PCM, devices in scribe-line/kerf, drop-in devices (EPO)