Class 257/E21.522 - Structural arrangement (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.521. This subclass
No. of patents: 23
Last issue date: 10/28/2008

Number	Title	Issue Date
7442559	Method for producing an optical or electronic module provided with a plastic package A method for producing an optical or electronic module provided with a plastic package including: providing at least one optical or electronic component, the component having an operative region, via which it is in operative connection with the surroundings in the f...	10/28/2008
7436077	Semiconductor device and method of manufacturing the same A semiconductor device includes a first surface faced to a mounting board when the semiconductor device is placed over the mounting board and a second surface opposed to the first surface. The semiconductor device also includes a position reference portion which is ...	10/14/2008
7432593	Semiconductor package assembly and method for electrically isolating modules A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394. ...	10/07/2008
7414299	Semiconductor package assembly and method for electrically isolating modules A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394. ...	08/19/2008
7381575	Device and method for detecting alignment of active areas and memory cell structures in DRAM devices A test device and method for detecting alignment of active areas and memory cell structures in DRAM devices with vertical transistors. In the test device, parallel first and second memory cell structures disposed in the scribe line region, each has a deep trench cap...	06/03/2008
7354842	Methods of forming conductive materials The invention includes a method of forming a metal-comprising mass for a semiconductor construction. A semiconductor substrate is provided, and a metallo-organic precursor is provided proximate the substrate. The precursor is exposed to a reducing atmosphere to rele...	04/08/2008
7335969	Method of monitoring introduction of interfacial species A method for monitoring a nitridation process, including: (a) providing a semiconductor substrate; (b) forming a first dielectric layer on a top surface of the substrate; (c) introducing a quantity of interfacial species into the substrate; (d) removing the first di...	02/26/2008
7317204	Test structure of semiconductor device A test structure of a semiconductor device is provided. The test structure includes a semiconductor substrate, a transistor which includes a gate electrode formed on first and second active regions defined within the semiconductor substrate, and first and second jun...	01/08/2008
7303929	Reloading of die carriers without removal of die carriers from sockets on test boards A method of testing microelectronic dies is described. A respective set of dies is inserted into die carrier bodies releasably held within a set of sockets secured to a burn-in board. A set of die carrier covers is closed, each die carrier cover being secured to a r...	12/04/2007
7271013	Semiconductor device having a bond pad and method therefor A bond pad (10) has a probe region (14) and a wire bond region (12) that are substantially non-overlapping. In one embodiment, the bond pad (10) is connected to a final metal layer pad (16) and extends over an interconnect region (...	09/18/2007
7271408	Semiconductor device test patterns and related methods for precisely measuring leakage currents in semiconductor cell transistors Semiconductor device test patterns are provided that include a word line on a semiconductor substrate and an active region having a first impurity doped region and a second impurity doped region in at the semiconductor substrate. A first self-aligned contact pad is ...	09/18/2007
7220606	Integrated circuit identification A method for marking a semiconductor wafer 302 includes the steps of: providing a reticle 300 including liquid crystal pixels; positioning the semiconductor wafer in proximity to the reticle; directing radiation through a first plurality of the pixels ...	05/22/2007
7148135	Method of designing low-power semiconductor integrated circuit A branching point on a wire is detected in the layout results S101. A delay amount of a route with a dummy buffer being inserted on a wire subsequent to the branching point S102 and that of the route without a dummy buffer being inserted are then calcu...	12/12/2006
7135345	Methods for processing semiconductor devices in a singulated form Improved methods and apparatus are provided for the handling and testing of semiconductor devices. One embodiment comprises a die carrier for one or more semiconductor dice having very fine pitch electrical I/O (input/output) elements. The semiconductor dice are tem...	11/14/2006
7105379	Implementation of protection layer for bond pad protection A method of protecting a bond pad during die-sawing comprising the following steps. A substrate having a bond pad formed thereover is provided. A bond pad protection layer is formed over the bond pad. The substrate is die-sawed and the bond pad protection layer is r...	09/12/2006
6858445	Method for adjusting the overlay of two mask planes in a photolithographic process for the production of an integrated circuit The present invention provides a method for optimizing the overlay adjustment of two mask planes in a photolithographic process for the production of an integrated circuit having the following steps: provision of a substrate (S) with at least one first mask plane (M...	02/22/2005
6281028	LED alignment points for semiconductor die Post-manufacturing analysis of a semiconductor device is enhanced via a method and system that use a light emitting diode (LED) formed in a semiconductor die during its manufacture. According to an example embodiment of the present invention, a LED is for...	08/28/2001
6274397	Method to preserve the testing chip for package's quality A method for eliminating metal line corrosion for semiconductor packages where exposed metal lines are exposed to the atmosphere for an extended period of time. A passivation layer is deposited over the active die of the semiconductor package, a layer of ...	08/14/2001
5981370	Method for maximizing interconnection integrity and reliability between integrated circuits and external connections A method of fabricating a semiconductor device which includes providing a shaped bond pad, preferably rectangular or oval. A cavity followed by a hill are formed in the bond pad by performing a probe test at one end portion of the bond pad. Then a ball bo...	11/09/1999
5418383	Semiconductor device capable of previously evaluating characteristics of power output element At least one power output element made of an insulated gate semiconductor element, a surge protection element for an input electrode of the power output element, and a circuit element block for controlling the power output element, are formed on the same ...	05/23/1995
5319224	Integrated circuit device having a geometry to enhance fabrication and testing and manufacturing method thereof A method of manufacturing a plurality of integrated circuit devices includes the steps as follows. First, a predetermined plurality number of bonding pads (11, 21) in a predetermined geometry are formed on the surface of each of a plural number of substra...	06/07/1994
5304738	System for protecting leads of a semiconductor chip package during testing, burn-in and handling After a semiconductor die is placed onto a leadframe and electrically connected to the die, the die and the ends of the leads adjacent to the die are encased in a packaged body. The exposed ends of the leads are trimmed so that the leads are of desired le...	04/19/1994
5221812	System for protecting leads to a semiconductor chip package during testing, burn-in and handling After a semiconductor die is placed onto a leadframe and electrically connected to the die, the die and the ends of the leads adjacent to the die are encased in a packaged body. The exposed ends of the leads are trimmed so that the leads are of desired le...	06/22/1993

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Class 257/E21.522 - Structural arrangement (EPO)