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| Number | Title | Issue Date |
| 7419852 | Low temperature methods of forming back side redistribution layers in association with through wafer interconnects, semiconductor devices including same, and assemblies Low temperature processed back side redistribution lines (RDLs) are disclosed. Low temperature processed back side RDLs may be electrically connected to the active surface devices of a semiconductor substrate using through wafer interconnects (TWIs). The TWIs may be... | 09/02/2008 |
| 7397132 | Semiconductor device Disclosed is a semiconductor device including an organic material substrate, a semiconductor chip flip chip connected to substantially a center of one surface of the organic material substrate, and a semiconductor package mounted on another surface of the organic ma... | 07/08/2008 |
| 7394151 | Semiconductor package with plated connection A semiconductor package and method for making a semiconductor package are disclosed. The semiconductor package has a top surface and a mounting surface and includes a die, a conducting connecting material, a plating material and an insulating material. The die has a... | 07/01/2008 |
| 7390735 | High temperature, stable SiC device interconnects and packages having low thermal resistance A method of forming packages containing SiC or other semiconductor devices bonded to other components or conductive surfaces utilizing transient liquid phase (TLP) bonding to create high temperature melting point bonds using in situ formed ternary or quaternary mixt... | 06/24/2008 |
| 7391122 | Techniques for flip chip package migration Techniques for integrated circuit packaging in a flip chip configuration that ensures a migration path between related integrated circuits and utilizes core I/O (or area I/O) are provided. An integrated circuit, having a superset of functional circuit elements as co... | 06/24/2008 |
| 7378727 | Memory device and a method of forming a memory device A memory device includes a semiconductor substrate having a surface, a plurality of first and second conductive lines, a plurality of memory cells, and a plurality of landing pads. Each of the first conductive lines has a line width wb and two neighboring ones of th... | 05/27/2008 |
| 7375422 | Stacked-type semiconductor package Corresponding parts to a first path portion in a first signal transmission path to a first semiconductor chip are an interconnection member and a second path portion a second signal transmission path to a second semiconductor chip and are not formed on the first tap... | 05/20/2008 |
| 7361530 | Method of fabricating a semiconductor integrated circuit that includes patterning a semiconductor substrate with a first photomask that uses metal for blocking light and patterning the same substrate with a second photomask that uses organic resin for blocking light Productivity of a semiconductor integrated circuit device is improved. According to how many times the photomask is used, a photomask having an opaque pattern made of metal and a photomask having an opaque pattern made of a resist film are properly used, and thereby... | 04/22/2008 |
| 7355276 | Thermally-enhanced circuit assembly A circuit assembly for mounting one or more integrated circuits that effectively dissipates heat generated by the integrated circuits, and a corresponding method for fabricating such a circuit assembly. The circuit assembly comprises a substrate, a thermally-conduct... | 04/08/2008 |
| 7341890 | Circuit board with built-in electronic component and method for manufacturing the same A circuit board with an built-in electronic component according to the present invention includes an insulating layer, a first wiring pattern provided on a first main surface of the insulating layer, a second wiring pattern provided on a second main surface differen... | 03/11/2008 |
| 7332424 | Fluxless solder transfer and reflow process Disclosed is a new process that permits the transfer and reflow of solder features produced by Injection Molded Solder (IMS) from a mold plate to a solder receiving substrate without the use of flux. Several embodiments produce solder transfer and reflow separately ... | 02/19/2008 |
| 7329563 | Method for fabrication of wafer level package incorporating dual compliant layers A method is provided for forming wafer level package that incorporates dual compliant layers and a metal cap layer on top of I/O pads. The wafer level package includes a plurality of metal cap layers formed on top of a plurality of I/O pads to function as stress buf... | 02/12/2008 |
| 7320940 | Method for manufacturing electronic device including package In a method for manufacturing an acceleration sensor device, a lid for covering an opening of a package body is prepared by stamping. The lid is plated and plating films are formed on surfaces of the lid. The burrs formed on the surfaces of the lid in the plating pr... | 01/22/2008 |
| 7321165 | Semiconductor device and its manufacturing method In a semiconductor device in which a plurality of substrates each mounting a semiconductor chip are stacked, one ends of the leads formed on the substrates are connected to the semiconductor chip and the other ends thereof are connected to connection terminals of th... | 01/22/2008 |
| 7319049 | Method of manufacturing an electronic parts packaging structure A method of manufacturing an electronic parts packaging structure of the present invention, includes the steps of forming a first uncured resin layer on a substrate, arranging an electronic parts on the first uncured resin layer, forming a second uncured resin layer... | 01/15/2008 |
| 7317257 | Inhibiting underfill flow using nanoparticles A method and apparatus for inhibiting the flow of a flowable adhesive material disposed adjacent to a substrate. A chip component is disposed adjacent to a substrate and a plurality of nanoparticles are disposed and cured adjacent to the substrate and proximate to t... | 01/08/2008 |
| 7312533 | Electronic component with flexible contacting pads and method for producing the electronic component An electronic component has an electronic circuit and a rubber-elastic elevation. The rubber-elastic elevation is formed of an insulating rubber-elastic material disposed on a surface of the electronic component and has a conductive land on its crest. The rubber-ela... | 12/25/2007 |
| 7304391 | Modified chip attach process and apparatus A method of packaging a die includes reflowing the solder to electrically connect the die to a substrate at a first temperature, cooling the die and substrate to a second temperature, and placing a heated epoxy in contact with the die and the substrate. The method a... | 12/04/2007 |
| 7300863 | Circuit chip connector and method of connecting a circuit chip An interposer and a method of manufacturing a flexible radio frequency (RF) type device having an IC and thin film circuits, such as an antenna. The device is made by using an easy-to-insert interposer subassembly with pre-positioned ICs to mechanically and electric... | 11/27/2007 |
| 7294529 | Method for embedding a component in a base This publication discloses a method, in which the semiconductor components forming part of an electronic circuit, or at least some of them, are embedded in a base, such as a circuit board, during the manufacture of the base, when part of the base structure is, as it... | 11/13/2007 |
| 7291916 | Signal transmission structure and circuit substrate thereof A signal transmission structure suitable for a multi-layer circuit substrate comprising a core layer and at least a dielectric layer is provided. The signal transmission structure according to the present invention comprises a first via landing pad and a reference p... | 11/06/2007 |
| 7282395 | Method of making exposed pad ball grid array package A method of making an exposed-pad ball-grid array package (11) includes applying a conductive sheet (16) to an adhesive tape (18). Stamping the conductive sheet (16) to form a die pad (24) and separating the remainder (26) o... | 10/16/2007 |
| 7276800 | Carrying structure of electronic components A carrying structure of electronic components is proposed. The carrying structure includes at least one supporting board with at least one cavity disposed thereon, at least one adhesive layer formed on the supporting board, and at least one electronic component havi... | 10/02/2007 |
| 7276794 | Junction-isolated vias A process for forming a junction-isolated, electrically conductive via in a silicon substrate and a conductive apparatus to carry electrical signal from one side of a silicon wafer to the other side are provided. The conductive via is junction-isolated from the bulk... | 10/02/2007 |
| 7271030 | Direct bumping on integrated circuit contacts enabled by metal-to-insulator adhesion A semiconductor device including a contact pad and circuit metallization on the surface of an integrated circuit (IC) chip comprises a stack of protection layers over the surface of the chip. The stack consists of a first inorganic layer (303, preferably sili... | 09/18/2007 |
| 7271495 | Chip bond layout for chip carrier for flip chip applications A chip carrier for flip chip applications, according to the present invention, provides peripheral bumps and inner bumps. The inputs and outputs related to the inner bumps are routed out on an additional wiring layer by means of vias. The proposed bond layout provid... | 09/18/2007 |
| 7259449 | Method and system for sealing a substrate A method of sealing a microelectromechanical system (MEMS) device from ambient conditions is described, wherein the MEMS device is formed on a substrate and a substantially hermetic seal is formed as part of the MEMS device manufacturing process. The method comprise... | 08/21/2007 |
| 7259454 | Semiconductor chip manufacturing method, semiconductor chip, semiconductor device manufacturing method, and semiconductor device The invention provides a semiconductor chip manufacturing method, including a step of forming a front-surface-side concave portion in a semiconductor substrate having a front surface and a rear surface, a functional device being formed on the front surface, the fron... | 08/21/2007 |
| 7253089 | Microfeature devices and methods for manufacturing microfeature devices Microfeature devices, microfeature workpieces, and methods for manufacturing microfeature devices and microfeature workpieces are disclosed herein. The microfeature workpieces have an integrated circuit, a surface, and a plurality of interconnect elements projecting... | 08/07/2007 |
| 7253503 | Integrated circuit device packages and substrates for making the packages Integrated circuit device packages and substrates for making the packages are disclosed. One embodiment of a substrate includes a planar sheet of polyimide having a first surface, an opposite second surface, and apertures between the first and second surfaces. A pla... | 08/07/2007 |
| 7241641 | Attachment of integrated circuit structures and other substrates to substrates with vias Vias (210, 210B) are formed in a surface of a substrate. At least portions of contact pads (139, 350) are located in the vias. Contact pads (150, 340) of an integrated circuit structure are inserted into the vias and attached to the contact pads... | 07/10/2007 |
| 7239023 | Package assembly for electronic device A buffer layer is formed on a substrate and then electronic devices are packed on the buffer layer in the present invention, and problems of lower hermeticity and complex process in the conventional arts can be avoided. Therefore, the present invention provides a pa... | 07/03/2007 |
| 7233060 | Module card structure A module card structure includes a structure, a first chip, a second chip, an adhesive layer, and a compound layer. The substrate has an upper surface on which a plurality of golden fingers are formed, and a lower surface. The first chip is mounted on the upper surf... | 06/19/2007 |
| 7229858 | Semiconductor wafer and semiconductor device manufacturing method using the same In a method of manufacturing a semiconductor device, a semiconductor wafer is prepared that includes a plurality of IC chips, each having a circuit including a terminal for applying an electrical quantity to the circuit, and a switch electrically connected to the te... | 06/12/2007 |
| 7223633 | Method for solder crack deflection An apparatus that includes a first component defining an interior of the apparatus; a first solder composition exterior to the first component; a second solder composition exterior to the first solder composition and the first component; and a second component exter... | 05/29/2007 |
| 7221044 | Heterogeneous integrated high voltage DC/AC light emitter A single-chip integrated LED particularly adapted for direct use with a high voltage DC or AC power sources comprises a plurality of electrically isolated LEDs on a generally transparent substrate and bonded to electrically conductive elements on a thermally conduct... | 05/22/2007 |
| 7220622 | Method for attaching a semiconductor die to a substrate and heat spreader Disclosed are embodiments of a method of attaching a die to a substrate and a heat spreader to the die in a single heating operation. A number of conductive bumps extending from the die may also be reflowed during this heating operation. Other embodiments are descri... | 05/22/2007 |
| 7198984 | Semiconductor device and method of manufacture thereof, circuit board and electronic instrument A method of manufacturing a semiconductor device includes (a) interposing an adhesive between a surface of a substrate on which an interconnect pattern is formed and a surface of a semiconductor chip on which electrodes are formed; and (b) applying pressure between ... | 04/03/2007 |
| 7199037 | Microfeature devices and methods for manufacturing microfeature devices Microfeature devices, microfeature workpieces, and methods for manufacturing microfeature devices and microfeature workpieces are disclosed herein. The microfeature workpieces have an integrated circuit, a surface, and a plurality of interconnect elements projecting... | 04/03/2007 |
| 7186584 | Integrated circuit chip, electronic device and method of manufacturing the same, and electronic instrument First and second electrodes and first and second electrical connection portions are overlapped and electrically connected. A first substrate includes: an attachment portion, a connection portion and an extension portion, the attachment portion being attached to the ... | 03/06/2007 |
