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| Number | Title | Issue Date |
| 7282447 | Method for an integrated circuit contact A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect... | 10/16/2007 |
| 7262134 | Microfeature workpieces and methods for forming interconnects in microfeature workpieces Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. In one embodiment, a method of forming an interconnect in a microfeature workpiece includes forming a hole extending through a t... | 08/28/2007 |
| 7244637 | Chip on board and heat sink attachment methods A process for forming a thermally enhanced Chip On Board semiconductor device with a heat sink is described. In one aspect, a thermally conductive-filled gel elastomer or a silicon elastomeric material or elastomeric material, if the material is to be removed, is ap... | 07/17/2007 |
| 7199059 | Method for removing polymer as etching residue A method for removing polymer as an etching residue is described. A substrate with polymer as an etching residue thereon is provided, and a hydrogen-containing plasma is used to treat the substrate. A wet clean step is then performed to remove the polymer from the s... | 04/03/2007 |
| 7169637 | One mask Pt/PCMO/Pt stack etching process for RRAM applications A one-mask etching method for use with a PCMO-containing RRAM to reduce stack side-wall residuals, includes preparing a substrate, taken from the group of substrates consisting of silicon, silicon dioxide and polysilicon; depositing a bottom electrode on the substra... | 01/30/2007 |
| 7084065 | Method for fabricating a semiconductor device A method for fabricating a semiconductor device that prevents the formation of a side etch caused by fluoride (CFx) produced when a barrier insulating film is etched. As shown in FIG. 1(G), an opening in the shape of a wiring trench is made in an i... | 08/01/2006 |
| 6887796 | Method of wet etching a silicon and nitrogen containing material The invention relates to a method of manufacturing a semiconductor device comprising the step of removing a silicon and nitrogen containing material by means of wet etching with an aqueous solution comprising hydrofluoric acid in a low concentration, the aqueous sol... | 05/03/2005 |
| 5693567 | Separately etching insulating layer for contacts within array and for peripheral pads A process of producing a product such as an x-ray sensor array performs two etching operations on an insulating layer to expose different parts of a conductive layer. One etch exposes part of the conductive layer in each unit of cell circuitry in the arra... | 12/02/1997 |
| 5157000 | Method for dry etching openings in integrated circuit layers A process is disclosed through which vias (50) can be formed by the reaction of an etchant species (52) with a mercury cadmium telluride (HgCdTe) or zinc sulfide (ZnS) layer (42). The activating gases (20) are preferably a hydrogen gas or a methane gas wh... | 10/20/1992 |
| 5110410 | Zinc sulfide planarization A procedure for planarizing a group II-VI composition which includes a resist and etch-back procedure wherein a thick resist coating relative to the degree of non-planarity is spun over a non-planar group II-VI layer to provide a planar resist surface. Th... | 05/05/1992 |
| 5017511 | Method for dry etching vias in integrated circuit layers A process is disclosed through which vias (50) can be formed by the reaction of an etchant species (52) with a mercury cadmium telluride (HgCdTe) or zinc sulfide (ZnS) layer (42). The activating gases (20) are preferably a hydrogen gas or a methane gas wh... | 05/21/1991 |
