Class 257/E21.446 - With PN homojunction gate (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.445. This
No. of patents: 32
Last issue date: 01/20/2004

Number	Title	Issue Date
6680522	Semiconductor device with reduced electrical variation An object of the invention is to minimize variation in characteristics of a vertical bipolar transistor. An insulating side wall spacer composed of a silicon nitride film 10 and a silicon oxide film 9 is formed on the side surface of an opening 101 formed...	01/20/2004
6580252	Boost circuit with normally off JFET An enhancement mode JFET as a switching device in a boost converter circuit combined with a single rectifier diode and an inductor. A control circuit coupled to the gate of the JFET switches the JFET between a current conducting state and a current blocki...	06/17/2003
6566936	Two terminal rectifier normally OFF JFET A two terminal semiconductor circuit that can be used to replace the semiconductor diodes used as rectifiers in conventional DC power supply circuits. Three semiconductor circuits that can efficiently supply the DC currents required in both discrete and i...	05/20/2003
6503782	Complementary accumulation-mode JFET integrated circuit topology using wide (>2eV) bandgap semiconductors A method and device produced for design, construction, and use of integrated circuits in wide bandgap semiconductors, including methods for fabrication of n-channel and p-channel junction field effect transistors on a single wafer or die, such that the pr...	01/07/2003
6486011	JFET structure and manufacture method for low on-resistance and low voltage application This invention discloses the present invention discloses a junction field effect transistor (JFET) device supported on a substrate. The JFET device includes a gate surrounded by a depletion region. As the distance between the gates is large enough, there ...	11/26/2002
6355513	Asymmetric depletion region for normally off JFET A semiconductor device efficiently providing the DC currents required in both discrete and integrated circuits operated at low DC supply voltages. The device disclosed in the present invention is an asymmetrical, enhancement mode, Junction Field Effect Tr...	03/12/2002
6251716	JFET structure and manufacture method for low on-resistance and low voltage application This invention discloses the present invention discloses a junction field effect transistor UFET) device supported on a substrate. The JFET device includes a gate surrounded by a depletion region. As the distance between the gates is large enough, there i...	06/26/2001
6020608	Junction-type field-effect transistor with improved impact-ionization resistance Junction-type field-effect transistors are disclosed exhibiting improved resistance to impact ionization. A p-type gate region is formed above an n-type channel region between an n-type drain region and an n-type source region each having a high impurity ...	02/01/2000
6020607	Semiconductor device having junction field effect transistors An N- type epitaxial layer is formed on a P type semiconductor substrate, and a P+ type insulative isolating layer is so formed as to reach the semiconductor substrate from the surface of the N- type epitaxial layer to ...	02/01/2000
5907168	Low noise Ge-JFETs A Germanium junction field effect transistor (Ge-JFET) is fabricated in a manner to produce low noise and which is particularly suitable for a cryogenic detector. The Ge-JFET in accordance with the present invention comprises a germanium base material on ...	05/25/1999
5639688	Method of making integrated circuit structure with narrow line widths In a sub-micron line width process, a first layer of polysilicon 13 is patterned into lines 1,2 spaced a predetermined distance. An oxide layer 11 is deposited. A second layer of polysilicon 14 is deposited on the insulating layer. A gate contact 19 or em...	06/17/1997
5605851	Method of forming semiconductor device with a buried junction A method is disclosed for forming a first region with conductivity of a first type and second, buried region with conductivity of a second type which forms a junction with the first region. By first and second doping steps, impurities of a first and a sec...	02/25/1997
5432377	Dielectrically isolated semiconductor device and a method for its manufacture A semiconductor device is supported by a semiconductor body which comprises a substrate, an oxide layer and a weakly doped monocrystalline wafer. Trenches for a dielectrically isolating layer which surrounds a component region are etched in the wafer. A f...	07/11/1995
5393998	Semiconductor memory device containing junction field effect transistor The miniaturization of junction field effect transistors constituting memory cells and higher integration of a dynamic semiconductor memory device are attained. Word lines composed of a p-type impurity diffusion layer are formed on an n-type silicon subst...	02/28/1995
5359214	Field effect devices formed from porous semiconductor materials A field effect transistor device constructed in accordance with the present invention includes a channel of semiconductive material such as silicon having at least one row of pores extending therethrough. Internal pn junctions are fabricated within the po...	10/25/1994
5321283	High frequency JFET The junction field effect transistors (JFETs) of this invention have improved breakdown voltage capability, reduced on-resistance and improved overdrive capability. The JFET on-resistance is decreased by ion-implanting an insulating layer covering a layer...	06/14/1994
5192699	Method of fabricating field effect transistors Method of fabricating a junction field effect transistor employing self-alignment techniques. The active regions of the device are defined by a relatively thin thermally-grown isolating silicon oxide layer at the surface of a silicon body. After the activ...	03/09/1993
5141880	Manufacturing method of a junction gate field effect transistor In a manufacturing method of a junction gate field effect transistor, impurities of a first conductivity type are first implanted at a predetermined concentration into a monocrystal silicon layer separately formed on a region to be used as an active regio...	08/25/1992
5126805	Junction field effect transistor with SiGe contact regions A junction field effect transistor, specifically a static induction transistor. Prior to metallization a thin layer of germanium is placed over the exposed silicon of the source and gate regions. The germanium is intermixed with the underlying silicon to ...	06/30/1992
5122851	Trench JFET integrated circuit elements A method and construction are disclosed to form a trench gate JFET transistor. The invention comprises forming a first trench in a semiconductor substrate, forming a gate channel about the trench and forming a conductive layer upon the surface of the gate...	06/16/1992
5120669	Method of forming self-aligned top gate channel barrier region in ion-implanted JFET An ion-implanted JFET has a channel barrier region at the top gate surface self-aligned to the source and drain, thereby maintaining sufficient separation between the channel barrier and the source and drain for attaining a high source/drain breakdown vol...	06/09/1992
5011785	Insulator assisted self-aligned gate junction A high transconductance, low capacitance, low leakage compound semiconduc junction field effect transistor (JFET) enhances the low leakage current while having the advantages of a self-aligned JFET including low capacitance and low source-drain resistanc...	04/30/1991
5010025	Method of making trench JFET integrated circuit elements A method and construction are disclosed to form a trench gate JFET transistor. The invention comprises forming a first trench in a semiconductor substrate, forming a gate channel about the trench and forming a conductive layer upon the surface of the gate...	04/23/1991
4983536	Method of fabricating junction field effect transistor A junction field effect transistor, specifically a static induction transistor. Prior to metallization a thin layer of germanium is placed over the exposed silicon of the source and gate regions. The germanium is intermixed with the underlying silicon to ...	01/08/1991
4959697	Short channel junction field effect transistor A junction field effect transistor fabricated by a simplified process for incorporation into an integrated circuit including bipolar transistors is disclosed. The JFET comprises an isolated gate region of a first conductivity type with a surface on the in...	09/25/1990
4914491	Junction field-effect transistors formed on insulator substrates A junction field effect transistor formed on insulator substrates particularly oxide substrates and having a polysilicon vertical control gate region formed of a cross member and two end members orthogonal thereto. The vertical control gate is formed over...	04/03/1990
4912053	Ion implanted JFET with self-aligned source and drain A method of fabricating I2 JFETs including separately and in combination out-diffusion of impurities from doped source and drain contact material to product self-aligned source and drains; using the source and drain contacts as mask to form a s...	03/27/1990
4900694	Process for the preparation of a multi-layer stacked junction typed thin film transistor using seperate remote plasma A process for the preparation of a multi-layers stacked junction typed thin film transister of which electric amplification factor (ଲ) at the time of the base electrode or the emitter electrode being grounded is about 10 and which has an excellent a...	02/13/1990
4845051	Buried gate JFET A process for manufacturing a JFET in accordance with our invention includes the steps of forming an N- layer (12) on an N+ substrate (10), and forming an N+ layer (14) on the N- layer. A plurality of trenches (19) are etched to extend through the N+ laye...	07/04/1989
4288800	Junction field effect transistor A vertical or horizontal type junction FET including a channel-gate structure formed by a double diffusion process in which two treatments for diffusing different impurities are executed through an identical opening provided in a diffusion mask. For fabri...	09/08/1981
4181542	Method of manufacturing junction field effect transistors A vertical or horizontal type junction FET including a channel-gate structure formed by a double diffusion process in which two treatments for diffusing different impurities are executed through an identical opening provided in a diffusion mask. For fabri...	01/01/1980
3951702	Method of manufacturing a junction field effect transistor A method of manufacturing a junction field effect transistor wherein after a P type pre-diffused layer is formed in an N type region constituting a back gate region of a junction field effect transistor, arsenic is selectively diffused into the P type pre...	04/20/1976

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Class 257/E21.446 - With PN homojunction gate (EPO)