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Class 257/E21.445 - With PN junction or heterojunction gate (EPO)


Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.4. This subclass
No. of patents: 6
Last issue date: 03/09/2004


NumberTitleIssue Date
6703688Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic p... 		03/09/2004
6677192Method of fabricating a relaxed silicon germanium platform having planarizing for high speed CMOS electronics and high speed analog circuits
Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic p... 		01/13/2004
6646322Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic p... 		11/11/2003
6593641Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic p... 		07/15/2003
5075746Thin film field effect transistor and a method of manufacturing the same
A thin film field effect transistor comprising a source electrode and a drain electrode joined to a first semiconductor layer respectively through first and second portions of a second doped semiconductor layer, a gate insulating layer, and a gate electro... 		12/24/1991
4700461Process for making junction field-effect transistors
A self-aligned integrated JFET device is described wherein an oxide extension region and a doped polysilicon gate is used as part of a self-aligned mask to form drain and source regions. Asymmetric JFETs for power circuit applications can be made in accor... 		10/20/1987
 
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