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| Number | Title | Issue Date |
| 7435628 | Method of forming a vertical MOS transistor A vertical MOS transistor has a source region, a channel region, and a drain region that are vertically stacked, and a trench that extends from the top surface of the drain region through the drain region, the channel region, and partially into the source region. Th... | 10/14/2008 |
| 7432179 | Controlling gate formation by removing dummy gate structures A method of forming semiconductor structures comprises following steps. A gate dielectric layer is formed over a substrate in an active region. A gate electrode layer is formed over the gate dielectric layer. A first photo resist is formed over the gate electrode la... | 10/07/2008 |
| 7416931 | Methods for fabricating a stress enhanced MOS circuit Methods are provided for fabricating a stress enhanced MOS circuit. One method comprises the steps of depositing a stressed material overlying a semiconductor substrate and patterning the stressed material to form a stressed dummy gate electrode overlying a channel ... | 08/26/2008 |
| 7405116 | Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selectiv... | 07/29/2008 |
| 7402494 | Method for fabricating high voltage semiconductor device A method for fabricating a high voltage semiconductor device, which comprises a semiconductor substrate; a gate insulation layer formed on the semiconductor substrate; and a gate electrode formed on the gate insulation layer, comprising: forming a mask pattern on th... | 07/22/2008 |
| 7396730 | Integrated circuit devices including an L-shaped depletion barrier layer adjacent opposite sides of a gate pattern and methods of forming the same Integrated circuit devices include an integrated circuit substrate having a channel region therein. A gate pattern is disposed on a top surface of the channel region. A depletion barrier layer covers a surface of the integrated circuit substrate adjacent opposite si... | 07/08/2008 |
| 7388257 | Multi-gate device with high k dielectric for channel top surface A multi-gate device has a high-k dielectric layer for a top channel of the gate and a protective layer for use in a finFET device. The high-k dielectric layer is placed on the top surface of the channel of the finFET and may reduce or eliminate silicon consumption i... | 06/17/2008 |
| 7374986 | Method of fabricating field effect transistor (FET) having wire channels In a field effect transistor (FET), and a method of fabricating the same, the FET includes a semiconductor substrate, source and drain regions formed on the semiconductor substrate, a plurality of wire channels electrically connecting the source and drain regions, t... | 05/20/2008 |
| 7371626 | Method for maintaining topographical uniformity of a semiconductor memory array A semiconductor device includes a memory array having a plurality of non-volatile memory cells. Each non-volatile memory cell of the plurality of non-volatile memory cells has a gate stack. The gate stack includes a control gate and a discrete charge storage layer s... | 05/13/2008 |
| 7358567 | High-voltage MOS device and fabrication thereof A HV-MOS device is described, including a substrate, a gate dielectric layer and a gate, a channel region, two doped regions as a source and a drain, a field isolation layer between the gate and at least one of the two doped regions, a drift region and a modifying d... | 04/15/2008 |
| 7354817 | Semiconductor device, manufacturing method thereof, and CMOS integrated circuit device A semiconductor device includes a semiconductor substrate. A gate electrode is formed on the semiconductor substrate via a gate insulating film. A source region and a drain region of a first conductivity type are formed on the first side and the second side of the g... | 04/08/2008 |
| 7232731 | Method for fabricating transistor of semiconductor device A method for fabricating a transistor of semiconductor is disclosed. A disclosed method comprises: forming an STI structure and a well region in a silicon substrate; forming a first dummy gate electrode including spacers and a first gate oxide layer on the well regi... | 06/19/2007 |
| 7211492 | Self aligned metal gates on high-k dielectrics A method for forming a transistor including a self aligned metal gate is provided. According to various method embodiments, a high-k gate dielectric is formed on a substrate and a sacrificial carbon gate is formed on the gate dielectric. Sacrificial carbon sidewall ... | 05/01/2007 |
| 7195999 | Metal-substituted transistor gates One aspect of this disclosure relates to a method for forming a transistor. According to various method embodiments, a gate dielectric is formed on a substrate, a substitutable structure is formed on the gate dielectric, and source/drain regions for the transistor a... | 03/27/2007 |
| 7179714 | Method of fabricating MOS transistor having fully silicided gate There is provided a method of fabricating a MOS transistor having a fully silicided gate, including forming a gate pattern and gate spacers on a semiconductor substrate, the gate pattern including a lower gate pattern, an insulating layer pattern, and an upper gate ... | 02/20/2007 |
| 7176075 | Field effect transistor and method of fabrication The present invention is a novel field effect transistor having a channel region formed from a narrow bandgap semiconductor film formed on an insulating substrate. A gate dielectric layer is formed on the narrow bandgap semiconductor film. A gate electrode is then f... | 02/13/2007 |
| 7166506 | Poly open polish process A method of fabricating microelectronic structure using at least two material removal steps, such as for in a poly open polish process, is disclosed. In one embodiment, the first removal step may be chemical mechanical polishing (CMP) step utilizing a slurry with hi... | 01/23/2007 |
| 7157345 | Source side injection storage device and method therefor A memory charge storage device has regions of sacrificial material overlying a substrate (12). For each memory cell a first doped region (20) and a second doped region (24) are formed within the substrate and on opposite sides of one (16)... | 01/02/2007 |
| 7157378 | Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, forming a trench within the dielectric layer, and forming a high-k gate dielectric layer within the trench. After forming a first metal layer on... | 01/02/2007 |
| 7129152 | Method for fabricating a short channel field-effect transistor A method for fabricating a short channel field-effect transistor is presented. A sublithographic gate sacrificial layer is formed, as are spacers at the side walls of the gate sacrificial layer. The gate sacrificial layer is removed to form a gate recess and a gate ... | 10/31/2006 |
| 6950362 | Semiconductor memory device A semiconductor memory device capable of enhancing a production yield is provided. A dummy control circuit activates a first dummy column including a plurality of dummy cells placed at a position close to a row decoder in a row direction and a second dummy column in... | 09/27/2005 |
| 6696725 | Dual-gate MOSFET with channel potential engineering A semiconductor device with reduced hot carrier injection and punch through is formed with a dual gate electrode comprising edge conductive portions, a central conductive portion, and dielectric sidewall spacers formed between the edge conductive portions... | 02/24/2004 |
| 6690047 | MIS transistor having a large driving current and method for producing the same In a MIS transistor, the top surfaces of source/drain regions (S/D diffusion layers) formed on a semiconductor substrate 1 are arranged nearer to a gate electrode than a channel plane on the semiconductor substrate, and the top surfaces of the source/drai... | 02/10/2004 |
| 6680243 | Shallow junction formation A method for forming shallow junctions in a substrate. The substrate is masked with a first mask to selectively cover first portions of the substrate and selectively expose second portions of the substrate. A first dopant is implanted substantially within... | 01/20/2004 |
| 6677652 | Methods to form dual metal gates by incorporating metals and their conductive oxides Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Oxygen ions ar... | 01/13/2004 |
| 6677646 | Method and structure of a disposable reversed spacer process for high performance recessed channel CMOS A high-performance recessed channel CMOS device including an SOI layer having a recessed channel region and adjoining extension implant regions and optional halo implant regions; and at least one gate region present atop the SOI layer and a method for fab... | 01/13/2004 |
| 6673712 | Method of forming dual-implanted gate and structure formed by the same A method of forming a dual-implanted gate and a structure formed by the same. Stack structures comprising a polysilicon layer, a sacrificial layer and a mask layer are formed over a substrate with a gate oxide layer thereon. A dielectric layer is formed o... | 01/06/2004 |
| 6674135 | Semiconductor structure having elevated salicided source/drain regions and metal gate electrode on nitride/oxide dielectric A semiconductor structure an a process for its manufacture. First and second gate dielectric layers are formed on a semiconductor substrate between nitride spacers, and a metal gate electrode is formed on the gate dielectric layers. Lightly-doped drain re... | 01/06/2004 |
| 6673683 | Damascene gate electrode method for fabricating field effect transistor (FET) device with ion implanted lightly doped extension regions A method for forming a field effect transistor device within a semiconductor product employs a patterned dummy layer first as an ion implantation mask layer when forming a pair of source/drain regions, and then as a mandrel layer for forming a pair of pat... | 01/06/2004 |
| 6667199 | Semiconductor device having a replacement gate type field effect transistor and its manufacturing method The present invention provides a MISFET with a replacement gate electrode, which ensures large ON-current. A semiconductor device, in which on the substrate, first and second field effect transistors are formed, the first field effect transistor is a repl... | 12/23/2003 |
| 6667246 | Wet-etching method and method for manufacturing semiconductor device A substrate with a metal oxide film deposited thereon is annealed, and then the surface of the metal oxide film is exposed to a plasma, after which the metal oxide film is removed by wet-etching.... | 12/23/2003 |
| 6664150 | Active well schemes for SOI technology A semiconductor device fabricated on a silicon-on-insulator substrate and having an active well scheme as well as methods, including a non-self-aligned and self-aligned, of fabricating such a device are disclosed herein. The semiconductor device includes ... | 12/16/2003 |
| 6664592 | Semiconductor device with groove type channel structure A semiconductor device includes a semiconductor substrate, a gate insulator film formed on a bottom surface and a side surface of a groove formed in the semiconductor substrate, a gate electrode having a lower portion buried in the groove on whose bottom ... | 12/16/2003 |
| 6664160 | Gate structure with high K dielectric A method for forming a gate structure beginning with a semiconductor substrate provided with an isolation region formed therein. An HfO2 layer and a conductive layer are formed on the semiconductor substrate, subsequently. The conductive layer ... | 12/16/2003 |
| 6664154 | Method of using amorphous carbon film as a sacrificial layer in replacement gate integration processes An exemplary embodiment relates to a method of using amorphous carbon in replacement gate integration processes. The method can include depositing an amorphous carbon layer above a substrate, patterning the amorphous carbon layer, depositing a dielectric ... | 12/16/2003 |
| 6664143 | Methods of fabricating vertical field effect transistors by conformal channel layer deposition on sidewalls Vertical field effect transistors are fabricated by depositing a vertical channel on a microelectronic substrate at a thickness along the microelectronic substrate that is independent of lithography, the vertical channel extending orthogonal to the microe... | 12/16/2003 |
| 6664195 | Method for forming damascene metal gate The present invention relates to a method of forming a damascene gate electrode of highly integrated MOS transistor capable of easily removing a dummy polysilicon layer. The disclosed comprises the steps of forming a dummy gate insulating layer and a poly... | 12/16/2003 |
| 6660600 | Methods of forming integrated circuitry, methods of forming elevated source/drain regions of a field effect transistor, and methods of forming field effect transistors Methods of forming integrated circuitry, methods of forming elevated source/drain regions, and methods of forming field effect transistors are described. In one embodiment, a transistor gate line is formed over a semiconductive substrate. A layer comprisi... | 12/09/2003 |
| 6660573 | Method of forming a gate electrode in a semiconductor device and method of manufacturing a non-volatile memory device using the same A method of forming a gate electrode, capable of minimizing a resistance difference between the gate electrodes and a method of forming a non-volatile memory device using the same, wherein an oxide film pattern, a polysilicon layer pattern and a hard mask... | 12/09/2003 |
| 6660596 | Double planar gated SOI MOSFET structure A double gated silicon-on-insulator (SOI) MOSFET is fabricated by using a mandrel shallow trench isolation formation process, followed by a damascene gate. The double gated MOSFET features narrow diffusion lines defined sublithographically or lithographic... | 12/09/2003 |
