Bizarre Patents
A simulation environment for the sport of boxing utilizing a robotic machine interface system which carries a person
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7435669 | Method of fabricating transistor in semiconductor device A method of fabricating a transistor in a semiconductor device. A gate oxide layer and a gate are formed on a semiconductor substrate. An oxide layer and a silicon nitride layer are stacked on the substrate. The stacked oxide and silicon nitride layers are etched ba... | 10/14/2008 |
| 7432180 | Method of fabricating a nickel silicide layer by conducting a thermal annealing process in a silane gas A method of fabricating a semiconductor device comprises the step of forming a nickel monosilicide layer selectively over a silicon region defined by an insulation film by a self-aligned process. The self-aligned process comprises the steps of forming a metallic nic... | 10/07/2008 |
| 7429525 | Fabrication process of a semiconductor device A method of fabricating a semiconductor device includes the steps of forming a metallic nickel film on a silicon substrate such that the metallic nickel film covers an insulation film on the silicon substrate and a silicon surface of the silicon substrate, annealing... | 09/30/2008 |
| 7422942 | Method for fabricating a semiconductor device having an insulation film with reduced water content A semiconductor device having a self-aligned contact hole is formed by providing a side wall oxide film on a gate electrode, covering the gate electrode and the side wall oxide film by an oxide film and further covering the oxide film by a nitride film, wherein the ... | 09/09/2008 |
| 7402520 | Edge removal of silicon-on-insulator transfer wafer A silicon-on-insulator transfer wafer having a front surface with a circumferential lip around a circular recess is polished. In one version, the circular recess on the front surface of the wafer is masked by filling the recess with spin-on-glass. The front surface ... | 07/22/2008 |
| 7396764 | Manufacturing method for forming all regions of the gate electrode silicided The technology which can improve the performance of a MOS transistor in which all the regions of the gate electrode were silicided is offered. A gate insulating film and a gate electrode of an nMOS transistor are laminated and formed in this order on a semico... | 07/08/2008 |
| 7384852 | Sub-lithographic gate length transistor using self-assembling polymers A semiconductor structure including at least one transistor located on a surface of a semiconductor substrate, wherein the at least one transistor has a sub-lithographic channel length, is provided. Also provided is a method to form such a semiconductor structure us... | 06/10/2008 |
| 7371599 | Image sensor and method of forming the same An image sensor includes a semiconductor substrate, a photo receiving area in the semiconductor substrate, a gate electrode installed in a lateral side of the photo receiving area on the semiconductor substrate, and a patterned dielectric layer covering the gate ele... | 05/13/2008 |
| 7368363 | Method of manufacturing semiconductor device and method of treating semiconductor surface A method of manufacturing a semiconductor device includes the steps of: exposing a semiconductor surface of a substrate; annealing the substrate in a hydrogen atmosphere at a hydrogen pressure between 200 Torr and 760 Torr and a temperature between 1000° C. and 105... | 05/06/2008 |
| 7364995 | Method of forming reduced short channel field effect transistor A method for manufacturing a semiconductor device capable of reducing a short channel effect, whereby the semiconductor device includes a pair of impurity regions for a source and a drain formed on a semiconductor substrate, a gate having a gate electrode used to co... | 04/29/2008 |
| 7348248 | CMOS transistor with high drive current and low sheet resistance A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate dielectric over a substrate, a gate electrode over the gate dielectric, a slim gate spacer along a side of the gate electrode, and a source/drain re... | 03/25/2008 |
| 7344984 | Technique for enhancing stress transfer into channel regions of NMOS and PMOS transistors A method and a semiconductor device are provided in which respective contact layers having a specific intrinsic stress may be directly formed on respective metal silicide regions without undue metal silicide degradation during an etch process for removing an unwante... | 03/18/2008 |
| 7344932 | Use of silicon block process step to camouflage a false transistor A technique for and structures for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is n... | 03/18/2008 |
| 7320939 | Semiconductor device fabricated by a method of reducing the contact resistance of the connection regions A semiconductor device, fabricated by a method, having a semiconductor structure with a silicon region which forms at least one connection region in and/or on a surface of a substrate is disclosed. In one embodiment, the method includes i) forming, at least at the s... | 01/22/2008 |
| 7309649 | Method of forming closed air gap interconnects and structures formed thereby A method to form a closed air gap interconnect structure is described. A starting structure made of regions of a permanent support dielectric under the interconnect lines and surrounding interconnect vias with one or more sacrificial dielectrics present in the remai... | 12/18/2007 |
| 7309637 | Method to enhance device performance with selective stress relief A structure and method of fabrication of a semiconductor device having a stress relief layer under a stress layer in one region of a substrate. In a first example, a stress relief layer is formed over a first region of the substrate (e.g., PFET region) and not over ... | 12/18/2007 |
| 7256096 | Semiconductor device having a dual-damascene gate and manufacturing method thereof A method of manufacturing a semiconductor device having a dual-damascene gate including forming LDD regions by forming a gate oxide film on a semiconductor substrate, and by implanting lowly-concentrated impurities in the semiconductor substrate in accordance with a... | 08/14/2007 |
| 7244996 | Structure of a field effect transistor having metallic silicide and manufacturing method thereof A field effect transistor having metallic silicide layers is formed in a semiconductor layer on an insulating layer of an SOI substrate. The metallic silicide layers are composed of refractory metal and silicon. The metallic silicide layers extend to bottom surfaces... | 07/17/2007 |
| 7223662 | Method of forming an epitaxial layer for raised drain and source regions by removing surface defects of the initial crystal surface By substantially amorphizing a selectively epitaxially grown silicon layer used for forming a raised drain and source region and a portion of the underlying substrate, or just the surface region of the substrate (prior to growing the silicon overlayer), the number o... | 05/29/2007 |
| 7220632 | Method of forming a semiconductor device and an optical device and structure thereof An integration process where a first semiconductor protective layer and a second semiconductor protective layer are formed to protect the first and second semiconductor materials, respectfully, during processing to form an optical device, such as a photodetector, an... | 05/22/2007 |
| 7220623 | Method for manufacturing silicide and semiconductor with the silicide The present invention is directed to a method of manufacturing silicide used to reduce a contact resistance at a contact of a semiconductor device and a semiconductor device with the silicide manufactured by the same method. The method comprises the steps of: (a) cl... | 05/22/2007 |
| 7217624 | Non-volatile memory device with conductive sidewall spacer and method for fabricating the same The present invention relates to a non-volatile memory device having conductive sidewall spacers and a method for fabricating the same. The non-volatile memory device includes: a substrate; a gate insulation layer formed on the substrate; a gate structure formed on ... | 05/15/2007 |
| 7217633 | Methods for fabricating an STI film of a semiconductor device Methods for fabricating a shallow trench isolation (STI) of a semiconductor device are disclosed. A disclosed method includes: forming a trench on a semiconductor substrate, forming an oxide layer on the semiconductor substrate and the trench, forming a photoresist ... | 05/15/2007 |
| 7211515 | Methods of forming silicide layers on source/drain regions of MOS transistors Methods of forming MOS transistors include forming lightly and heavily doped source/drain regions adjacent to one another in a substrate and a gate electrode with a sidewall spacer thereon. A salicide process is performed on a surface of the heavily doped source/dra... | 05/01/2007 |
| 7211491 | Method of fabricating gate electrode of semiconductor device A method of fabricating a gate electrode of a semiconductor device is disclosed. A disclosed method comprises growing a silicon epitaxial layer on a silicon substrate; making at least one trench through the epitaxial layer and filling the trench with a first oxide l... | 05/01/2007 |
| 7179739 | Methods of forming a semiconductor device including a metal silicide layer between a conductive plug and a bottom electrode of a capacitor Embodiments of the present invention include methods of forming a contact to a capacitor in a semiconductor device. A metal silicide layer is formed at a top surface of a conductive plug of the semiconductor device that is coupled to a bottom electrode of the capaci... | 02/20/2007 |
| 7169676 | Semiconductor devices and methods for forming the same including contacting gate to source Semiconductors having electrically coupled gate and impurity doped regions and methods for fabricating the same are provided. A method in accordance with an embodiment of the invention comprises forming a gate electrode overlying a substrate and an impurity doped re... | 01/30/2007 |
| 7148108 | Method of manufacturing semiconductor device having step gate Disclosed herein is a method of manufacturing a semiconductor device having a step gate, which can improve the refresh characteristics of the device. The method comprises the steps of: forming on a silicon substrate having active and field regions a first hard mask ... | 12/12/2006 |
| 7122449 | Methods of fabricating semiconductor structures having epitaxially grown source and drain elements Methods for fabricating facetless semiconductor structures using commercially available chemical vapor deposition systems are disclosed herein. A key aspect of the invention includes selectively depositing an epitaxial layer of at least one semiconductor material on... | 10/17/2006 |
| 7122871 | Integrated circuit field effect transistors including channel-containing fin having regions of high and low doping concentrations Integrated circuit field effect transistors include an integrated circuit substrate and a fin that projects away from the integrated circuit substrate, extends along the integrated circuit substrate, and includes a top that is remote from the integrated circuit subs... | 10/17/2006 |
| 7118954 | High voltage metal-oxide-semiconductor transistor devices and method of making the same A method for fabricating metal-oxide-semiconductor devices is provided. The method includes forming a gate dielectric layer on a substrate; depositing a polysilicon layer on the gate dielectric layer; forming a resist mask on the polysilicon layer; etching the polys... | 10/10/2006 |
| 6703296 | Method for forming metal salicide A method for forming a metal salicide layer on a shallow junction is described. A substrate having a gate structure thereon and a shallow junction therein is provided. An atomic layer deposition (ALD) process is then performed to deposit a tungsten salici... | 03/09/2004 |
| 6703291 | Selective NiGe wet etch for transistors with Ge body and/or Ge source/drain extensions The wet etch stage of the salicide process normally used to fabricate polysilicon and silicon-based semiconductor transistors may not be appropriate for germanium-based transistors because the wet etch chemicals at such temperatures will dissolve the germ... | 03/09/2004 |
| 6703648 | Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication A strained silicon p-type MOSFET utilizes a strained silicon channel region formed on a silicon germanium substrate. Silicon germanium regions are formed to the silicon germanium layer adjacent to ends of the strained silicon channel region, and shallow s... | 03/09/2004 |
| 6703281 | Differential laser thermal process with disposable spacers MOSFETs are fabricated with accurately defined, high and uniformly concentrated source/drain regions and extensions employing plural, sequential pre-amorphizing, implanting and laser thermal annealing steps with intervening spacer removal. Embodiments inc... | 03/09/2004 |
| 6699755 | Method for producing a gate A method for producing a gate on a semiconductor substrate. The semiconductor substratehas a first oxide layer, a conductive layer, a silicide layer, and a hard mask formed thereon. The method includes defining the hard mask to form a pattern of the gate,... | 03/02/2004 |
| 6696345 | Metal-gate electrode for CMOS transistor applications Described is a CMOS transistor structure with a multi-layered gate electrode structure and a method of fabrication. The gate electrode structure has a three-layered metallic gate electrode and a polysilicon layer. The first metallic layer acts as a barrie... | 02/24/2004 |
| 6696354 | Method of forming salicide A method of forming a salicide. A metal layer is formed on a silicon-based substrate comprising a gate with a spacer on the side wall of the gate and a source/drain is provided. Next, a first thermal treatment is performed to make the portions of the meta... | 02/24/2004 |
| 6690072 | Method and structure for ultra-low contact resistance CMOS formed by vertically self-aligned CoSi2 on raised source drain Si/SiGe device A method (and structure) of forming a vertically-self-aligned silicide contact to an underlying SiGe layer, includes forming a layer of silicon of a first predetermined thickness on the SiGe layer and forming a layer of metal on the silicon layer, where t... | 02/10/2004 |
| 6686274 | Semiconductor device having cobalt silicide film in which diffusion of cobalt atoms is inhibited and its production process In a semiconductor device having a cobalt silicide film, at least nickel or iron is contained in the cobalt silicide film for preventing the rise of resistance incidental to thinning of the film.... | 02/03/2004 |
