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| Number | Title | Issue Date |
| 7312138 | Semiconductor device and method of manufacture thereof A method of manufacturing a MOS transistor incorporating a silicon oxide film serving as a gate insulating film and containing nitrogen and a polycrystalline silicon film serving as a gate electrode and containing a dopant and arranged such that the gate electrode i... | 12/25/2007 |
| 7153748 | Semiconductor devices and methods for fabricating the same Semiconductor devices having an elevated contact region and methods of fabricating the same are disclosed. A disclosed semiconductor device includes a semiconductor substrate, a gate on the semiconductor substrate, spacers on sidewalls of the gate, an epitaxial laye... | 12/26/2006 |
| 6673663 | Methods of forming field effect transistors and related field effect transistor constructions Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ... | 01/06/2004 |
| 6548362 | Method of forming MOSFET with buried contact and air-gap gate structure A method of forming MOSFET with buried contacts and air-gap gate structure is disclosed. The method comprises following steps firstly, a gate is formed of pad oxide layer and a nitride layer sequentially on a silicon substrate, which has trench isolations... | 04/15/2003 |
| 6544827 | Metal-gate field effect transistor and method for manufacturing the same A metal gate MISFET comprises a metal gate electrode on a semiconductor substrate, a side wall insulation film, and a source-drain region which is formed on the surface of the semiconductor substrate on both sides of the side wall insulation film. Then, a... | 04/08/2003 |
| 6482691 | Seismic imaging using omni-azimuth seismic energy sources and directional sensing Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ... | 11/19/2002 |
| 6479858 | Method and apparatus for a semiconductor device with adjustable threshold voltage The present invention provides a semiconductor device with a channel length of approximately 0.05 microns. A semiconductor device according to the present invention, and a method for producing such a semiconductor device, comprises a control gate, a first... | 11/12/2002 |
| 6475852 | Method of forming field effect transistors and related field effect transistor constructions Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ... | 11/05/2002 |
| 6475874 | Damascene NiSi metal gate high-k transistor A method for implementing a self-aligned low temperature metal silicide gate is achieved by confining amorphous silicon within a recess overlying a channel and annealing to cause the amorphous silicon with its overlying low temperature silicidation metal ... | 11/05/2002 |
| 6472260 | Methods of forming field effect transistors and related field effect transistor constructions Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ... | 10/29/2002 |
| 6429110 | MOSFET with both elevated source-drain and metal gate and fabricating method A method of forming a transistor and a semiconductor-metal-oxide transistor. The method at least includes provides a substrate; covers the substrate by a doped amorphous polysilicon layer and a barrier layer in sequence, and removes part of the barrier la... | 08/06/2002 |
| 6413823 | Methods of forming field effect transistors Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ... | 07/02/2002 |
| 6410967 | Transistor having enhanced metal silicide and a self-aligned gate electrode A transistor and a method for making a transistor are described. A metal layer is formed upon a semiconductor substrate, and a masking layer is formed upon the metal layer. The masking layer is patterned to form an opening therein, and portions of the met... | 06/25/2002 |
| 6406957 | Methods of forming field effect transistors and related field effect transistor constructions Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ... | 06/18/2002 |
| 6400002 | Methods of forming field effect transistors and related field effect transistor constructions Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ... | 06/04/2002 |
| 6344382 | Methods of forming field effect transistors and related field effect transistor constructions Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ... | 02/05/2002 |
| 6342414 | Damascene NiSi metal gate high-k transistor A method for implementing a self-aligned low temperature metal silicide gate is achieved by confining a low temperature silicidation metal within a recess overlying a channel and annealing to cause the low temperature silicidation metal and its overlying ... | 01/29/2002 |
| 6335234 | Methods of forming field effect transistors and related field effect transistor constructions Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ... | 01/01/2002 |
| 6335246 | Methods of forming field effect transistors and related field effect transistor constructions Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ... | 01/01/2002 |
| 6319807 | Method for forming a semiconductor device by using reverse-offset spacer process A method for forming semiconductor devices is disclosed. The method of the present invention includes providing a semiconductor substrate, followed by forming shallow trench isolation (STI) process, and then a dummy gate is formed by silicon nitride layer... | 11/20/2001 |
| 6287953 | Minimizing transistor size in integrated circuits A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal space between gate and the local interconnects by fabricating the source and drain of the FET and the ... | 09/11/2001 |
| 6281101 | Process of forming metal silicide interconnects A process for forming a metal silicide interconnect includes applying a layer of polysilicon over a semiconductor layer. A layer of amorphous silicon is formed over the layer of polysilicon followed by a layer of metal, such as titanium, over the layer of... | 08/28/2001 |
| 6265272 | Method of fabricating a semiconductor device with elevated source/drain regions A fabrication process of forming a semiconductor device with elevated source/drain regions on a substrate is disclosed. The elevated portion of the source/drain regions is provided as a reactant for a later metallization process, thereby preventing the co... | 07/24/2001 |
| 6228729 | MOS transistors having raised source and drain and interconnects A process for fabricating a semiconductor device comprising a gate electrode, a raised source, a raised drain and an interconnect inlaid into an isolation region. A semiconductor device is fabricated by a process comprising the following steps: forming se... | 05/08/2001 |
| 6222240 | Salicide and gate dielectric formed from a single layer of refractory metal An integrated circuit fabrication process is provided for forming a metal oxide gate dielectric and salicide structures from a unitary layer of refractory metal. The refractory metal layer is placed upon a silicon-based substrate before the formation of t... | 04/24/2001 |
| 6218710 | Method to ensure isolation between source-drain and gate electrode using self aligned silicidation A MOSFET device fabricated by a method that reduces, the risk of gate to source and drain bridging, has been developed. The process features fabricating a polysilicon structure, which is wider at the top than at the bottom, with a source and drain region,... | 04/17/2001 |
| 6218690 | Transistor having reverse self-aligned structure A reverse self-aligned field effect transistor and a method of fabricating the same are provided. The reverse self-aligned transistor includes a source formed on an active region of a semiconductor substrate and a drain formed on the active region of the ... | 04/17/2001 |
| 6211025 | Method of making elevated source/drain using poly underlayer A transistor and a method of making the same are provided. The transistor includes a substrate and a gate dielectric layer positioned on the substrate that has first and second sidewall spacers. A gate electrode is positioned on the gate dielectric layer ... | 04/03/2001 |
| 6204137 | Method to form transistors and local interconnects using a silicon nitride dummy gate technique A new method of forming MOS transistors has been achieved. A pad oxide layer is grown. A silicon nitride layer is deposited. Trenches are etched for planned STI. A trench liner is grown inside of the trenches. A trench oxide layer is deposited filling the... | 03/20/2001 |
| 6146954 | Minimizing transistor size in integrated circuits A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal insulating space between polysilicon gate and the local interconnects by fabricating the source and dr... | 11/14/2000 |
| 6143593 | Elevated channel MOSFET The present invention provides a method of producing a semiconductor device (e.g., a Metal Oxide Semiconductor Field Effect Transistor (MOSFET)) with a gate length less than 0.25 microns using standard process techniques arranged in an unstandardized proc... | 11/07/2000 |
| 6127712 | Mosfet with buried contact and air-gap gate structure A MOSFET with buried contacts and air-gap gate structure is disclosed. The MOSFET comprises trench isolation regions on a silicon substrate. A poly gate on the active region is formed of a gate dielectric layer and a polysilicon layer, wherein the polysil... | 10/03/2000 |
| 6127233 | Lateral MOSFET having a barrier between the source/drain regions and the channel region A lateral MOSFET (100) and a method for making the same. A two layer raised source/drain region (106) is located adjacent a gate structure (112). The first layer (106a) of the raised source drain is initially doped p-type and the second layer (106b) of th... | 10/03/2000 |
| 6114208 | Method for fabricating complementary MOS transistor A method for fabricating complementary metal-oxide-semiconductor (CMOS) devices and circuits resulting therefrom are provided. The method includes forming the source and drain regions of the CMOS device by out-diffusion of ions injected into a conductive ... | 09/05/2000 |
| 6100161 | Method of fabrication of a raised source/drain transistor A method of fabricating a transistor, comprising the following steps. A silicon semiconductor substrate having a pad oxide portion within an active area is provided. A polysilicon layer is deposited over the silicon semiconductor substrate and over the pa... | 08/08/2000 |
| 6090691 | Method for forming a raised source and drain without using selective epitaxial growth A method for forming a raised source and drain structure without using selective epitaxial silicon growth. A semiconductor substrate is provided having one or more gate areas covered by dielectric structures. Doped polysilicon structures are adjacent to t... | 07/18/2000 |
| 6051473 | Fabrication of raised source-drain transistor devices A process in accordance with the invention enables the manufacturability of raised source-drain MOSFETs. In accordance with the invention, a raised source-drain material, having a window therein, is formed over the substrate. A gate oxide and window sidew... | 04/18/2000 |
| 6046098 | Process of forming metal silicide interconnects A process for forming a metal suicide interconnect includes applying a layer of polysilicon over a semiconductor layer. A layer of amorphous silicon is formed over the layer of polysilicon followed by a layer of metal, such as titanium, over the layer of ... | 04/04/2000 |
| 6025232 | Methods of forming field effect transistors and related field effect transistor constructions Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ... | 02/15/2000 |
| 6008097 | MOS transistor of semiconductor device and method of manufacturing the same The present invention relates to a MOS transistor of semiconductor device and method of manufacturing the same and, in particular, to MOS a transistor of semiconductor device and method of manufacturing the same which can reduce asymmetry of drain current... | 12/28/1999 |
