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| Number | Title | Issue Date |
| 7413957 | Methods for forming a transistor Methods are provided for depositing materials in forming semiconductor devices on a substrate, such as metal oxide transistors. In one embodiment, the invention generally provides a method of processing a substrate including forming a gate dielectric on a substrate ... | 08/19/2008 |
| 7413961 | Method of fabricating a transistor structure The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. There is provi... | 08/19/2008 |
| 7397091 | SiGe nickel barrier structure employed in a CMOS device to prevent excess diffusion of nickel used in the silicide material A CMOS device such as an NFET or a PFET and a method of forming a CMOS device are provided. The method begins by forming at least one patterned gate region atop a first semiconductor layer that includes silicon. Dielectric spacers are formed about exposed portions o... | 07/08/2008 |
| 7385261 | Extended drain metal oxide semiconductor transistor and manufacturing method thereof A MOS transistor having an extended drain structure and including a semiconductor substrate formed in a well of a first conductivity type. A gate insulating layer is formed on the substrate, a gate electrode is formed on the gate insulating layer, and a source regio... | 06/10/2008 |
| 7381623 | Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance The embodiments of the invention provide a method, etc. for a pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance. More specifically, one method begins by forming a first gate and a second ga... | 06/03/2008 |
| 7368792 | MOS transistor with elevated source/drain structure In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is fo... | 05/06/2008 |
| 7364957 | Method and apparatus for semiconductor device with improved source/drain junctions A semiconductor device with improved source/drain junctions and methods for fabricating the device are disclosed. A preferred embodiment comprises a MOS transistor with a gate structure overlying a substrate, lightly doped source/drain regions formed in the substrat... | 04/29/2008 |
| 7364976 | Selective etch for patterning a semiconductor film deposited non-selectively A method to selectively etch, and hence pattern, a semiconductor film deposited non-selectively is described. In one embodiment, a carbon-doped silicon film is deposited non-selectively such that the film forms an epitaxial region where deposited on a crystalline su... | 04/29/2008 |
| 7361973 | Embedded stressed nitride liners for CMOS performance improvement The present invention provides a semiconducting device including a gate region positioned on a mesa portion of a substrate; and a nitride liner positioned on the gate region and recessed surfaces of the substrate adjacent to the gate region, the nitride liner provid... | 04/22/2008 |
| 7354835 | Method of fabricating CMOS transistor and CMOS transistor fabricated thereby In a method of fabricating a CMOS transistor, and a CMOS transistor fabricated according to the method, the characteristics of first and second conductivity type MOS transistors are both simultaneously improved. At the same time, the fabrication process is simplifie... | 04/08/2008 |
| 7344951 | Surface preparation method for selective and non-selective epitaxial growth According to one embodiment of the invention, a surface preparation method for selective and non-selective epitaxial growth includes providing a substrate having a gate region, a source region, and a drain region, etching a first portion of the source region and the... | 03/18/2008 |
| 7265419 | Semiconductor memory device with cell transistors having electrically floating channel bodies to store data A semiconductor memory device includes: a semiconductor device base having an insulating substrate and a semiconductor layer overlying it; a cell array formed on the semiconductor device base with cell transistors disposed in such a manner that each of source and dr... | 09/04/2007 |
| 7223662 | Method of forming an epitaxial layer for raised drain and source regions by removing surface defects of the initial crystal surface By substantially amorphizing a selectively epitaxially grown silicon layer used for forming a raised drain and source region and a portion of the underlying substrate, or just the surface region of the substrate (prior to growing the silicon overlayer), the number o... | 05/29/2007 |
| 7195982 | Method for manufacturing anti-punch through semiconductor device A method for manufacturing an anti-punch through semiconductor device is described. The method is applied to a substrate having a plurality of device isolation structures in parallel arrangements and the upper surface of the device isolation structures is protruded ... | 03/27/2007 |
| 7193276 | Semiconductor devices with a source/drain regions formed on a recessed portion of an isolation layer Semiconductor devices and methods of fabricating semiconductor devices that include a substrate and a device isolation layer in the substrate that defines an active region of the substrate are provided. The device isolation layer has a vertically protruding portion ... | 03/20/2007 |
| 7118977 | System and method for improved dopant profiles in CMOS transistors According to one embodiment of the present invention, a method of forming a semiconductor device includes forming a gate stack on an outer surface of a semiconductor body. First and second sidewall bodies are formed on opposing sides of the gate stack. A first reces... | 10/10/2006 |
| 7118952 | Method of making transistor with strained source/drain A method of fabricating a transistor comprises the steps of: forming a gate electrode above a substrate made of a first semiconductor material having a first lattice spacing, forming recesses in the semiconductor substrate at respective locations where a source regi... | 10/10/2006 |
| 6670253 | Fabrication method for punch-through defect resistant semiconductor memory device A semiconductor device and a fabrication method thereof which can, for example, prevent a punch-through from occurring by forming oxide spacers around source/drain regions in a semiconductor substrate instead of forming a conventional halo ion implanting ... | 12/30/2003 |
| 6667516 | RF LDMOS on partial SOI substrate In the prior art LDMOSFET devices capable of handling high power have been made by locating the source contact on the bottom surface of the device, allowing for good heat sinking, with connection to the source region being made through a sinker. However, ... | 12/23/2003 |
| 6657223 | Strained silicon MOSFET having silicon source/drain regions and method for its fabrication A strained silicon MOSFET utilizes a strained silicon layer formed on a silicon germanium layer. Strained silicon and silicon germanium are removed at opposing sides of the gate and are replaced by silicon regions. Deep source and drain regions are implan... | 12/02/2003 |
| 6656845 | Method for forming semiconductor substrate with convex shaped active region Within a method for fabricating a semiconductor substrate while employing formed thereover a mask layer there is first employed the mask layer as an etch mask layer for forming a pair of isolation trenches within the semiconductor substrate and then later... | 12/02/2003 |
| 6653674 | Vertical source/drain contact semiconductor A semiconductor device is provided having angled dopant implantation and vertical trenches in the silicon on insulator substrate adjacent to the sides of a semiconductor gate. A second dopant implantation is in the exposed the source/drain junctions. Cont... | 11/25/2003 |
| 6649460 | Fabricating a substantially self-aligned MOSFET The present invention includes methods and structures for forming at least a substantially self-aligned MOSFET. According to the present invention, a method of fabricating a semiconductor device includes providing a substrate; providing first materials (s... | 11/18/2003 |
| 6649481 | Methods of fabricating a semiconductor device structure for manufacturing high-density and high-performance integrated-circuits The invention discloses methods of fabricating a semiconductor device structure having low source/drain junction capacitances and low junction leakage currents. The low source/drain junction capacitances are obtained by implementing in a self-aligned mann... | 11/18/2003 |
| 6624036 | Transistor in semiconductor device and method of manufacturing the same The present invention relates to a transistor in a semiconductor device and method of manufacturing the same. Therefore, the present invention can obtain an effect such as using a SOI substrate or a SIMOX substrate and can prevent a lowering in an electri... | 09/23/2003 |
| 6621131 | Semiconductor transistor having a stressed channel A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and... | 09/16/2003 |
| 6570233 | Method of fabricating an integrated circuit The invention provides a technology for reducing the direct contact resistance and for reducing the junction leak while maintaining the punch through margin. A semiconductor integrated circuit device is provided which comprises: a substrate; a transistor ... | 05/27/2003 |
| 6562707 | Method of forming a semiconductor device using selective epitaxial growth A method of forming a semiconductor device using selective epitaxial growth (SEG) is provided. This method includes forming an insulating layer pattern having a window on a semiconductor substrate. The window exposes a predetermined region of the semicond... | 05/13/2003 |
| 6563152 | Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel A method for forming a strain layer on an underside of a channel in an MOS transistor in order to produce a mechanical stress in the channel, increasing a mobility of carriers in the channel and an apparatus produced from such a method.... | 05/13/2003 |
| 6545327 | Semiconductor device having different gate insulating films with different amount of carbon A manufacturing method produces a semiconductor IC device which can maintain a low power consumption for electronic circuits and form gate-isolation layers of different thicknesses without increasing the manufacturing cost. The semiconductor IC device has... | 04/08/2003 |
| 6541343 | Methods of making field effect transistor structure with partially isolated source/drain junctions A microelectronic structure includes at least one source/drain terminal of a first conductivity type that is partially isolated from a region of semiconductor material of a second conductivity type. In a further aspect of the invention, a process for form... | 04/01/2003 |
| 6528855 | MOSFET having a low aspect ratio between the gate and the source/drain A MOSFET having a new source/drain (S/D) structure is particularly adapted to smaller feature sizes of modern CMOS technology. The S/D conductors are located on the shallow trench isolation (STI) to achieve low junction leakage and low junction capacitanc... | 03/04/2003 |
| 6518155 | Device structure and method for reducing silicide encroachment A semiconductor device having a novel spacer structure and method of fabrication. The present invention describes a semiconductor device which has an electrode with a first thickness. A silicide layer having a second thickness is formed on the electrode. ... | 02/11/2003 |
| 6518109 | Technique to produce isolated junctions by forming an insulation layer A method for isolating a source and a drain in an MOS transistor by forming an insulation layer adjacent to the source and an insulation layer adjacent to the drain, and an apparatus produced from such a method.... | 02/11/2003 |
| 6509241 | Process for fabricating an MOS device having highly-localized halo regions A process for fabricating an MOS device having a highly-localized halo region includes the formation of a first halo region at a first surface of a silicon substrate, and a second halo region at a second surface of the silicon substrate. The second surfac... | 01/21/2003 |
| 6506651 | Semiconductor device and manufacturing method thereof There are provide a semiconductor device capable of increasing the operating speed of MOS transistors and improving current driving capability, and a method of manufacturing such a semiconductor device. A semiconductor device comprises a silicon substrate... | 01/14/2003 |
| 6492216 | Method of forming a transistor with a strained channel A method of forming a tensile or compressive strained channel region for a semiconductor device, such as a MOSFET device, allowing improved carrier transport properties and increased device performance to be realized, has been developed. The method featur... | 12/10/2002 |
| 6483158 | Semiconductor memory device and fabrication method therefor A semiconductor device and a fabrication method thereof which can, for example, prevent a punch-through from occurring by forming oxide spacers around source/drain regions in a semiconductor substrate instead of forming a conventional halo ion implanting ... | 11/19/2002 |
| 6465311 | Method of making a MOSFET structure having improved source/drain junction performance A MOSFET structure having substantially reduced parasitic junction capacitance, relaxed thermal budget constraints and resiliency to hot carrier damage is disclosed. The MOSFET structure includes a gate stack that is disposed over a gate oxide that is in ... | 10/15/2002 |
| 6465296 | Vertical source/drain contact semiconductor A semiconductor device and manufacturing process therefor is provided in which angled dopant implantation is followed by the formation of vertical trenches in the silicon on insulator substrate adjacent to the sides of the semiconductor gate. A second dop... | 10/15/2002 |
