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...When G.G. Hubbard learned of his future son-in-law's invention, he called it "only a toy." His daughter was engaged to a young man named Alexander Graham Bell.
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| Number | Title | Issue Date |
| 7378318 | System and method for ensuring migratability of circuits by masking portions of the circuits while improving performance of other portions of the circuits A system and method for ensuring the migratability of circuits into future technologies while minimizing fabrication costs and maintaining or improving power efficiency are provided. A mask layer is introduced to portions of the integrated circuit prior to a stress ... | 05/27/2008 |
| 6515319 | Field-effect-controlled transistor and method for fabricating the transistor An active surface with a source area, a channel area and a drain area is provided in a semiconductor substrate. Each of the areas lie adjacent to a main surface of the semiconductor substrate. At least one trench is provided in the main surface of the sem... | 02/04/2003 |
| 6350641 | Method of increasing the depth of lightly doping in a high voltage device A method for fabricating a high vltage device with double diffusion structure provides a pad oxide layer on a silicon substrate. A silicon nitride layer is formed and patterned to expose isolation regions. A first mask covers the partial isolation regions... | 02/26/2002 |
| 6329256 | Self-aligned damascene gate formation with low gate resistance In order to form a self-aligned damascene gate which enables the resistance of the gate to be reduced, a thick layer of dielectric material is formed over a semiconductor substrate in which drain and source regions have previously been implanted and annea... | 12/11/2001 |
| 6323524 | Semiconductor device having a vertical active region and method of manufacture thereof A semiconductor device and method of manufacture thereof is provided. According to one embodiment, a semiconductor device is formed by forming a trench within a substrate. An oxide layer is formed within the trench and portions of the oxide layer are remo... | 11/27/2001 |
| 6225170 | Self-aligned damascene gate with contact formation In order to form a self-aligned damascene gate with an attendant contact or contacts, a thick layer of dielectric material is formed over a semiconductor substrate in which drain and source regions have previously been implanted and annealed. This dielect... | 05/01/2001 |
| 6144538 | High voltage MOS transistor used in protection circuits An electrostatic discharge (ESD) protection circuit is formed on a semiconductor wafer. The semiconductor wafer comprises a substrate, an active region having a doped area formed in a predetermined area on the surface of the substrate, and a field oxide l... | 11/07/2000 |
| 6140193 | Method for forming a high-voltage semiconductor device with trench structure A method for forming high-voltage semiconductor devices that have trench structure, substantially facilitating the integration of the high-voltage devices and the low-voltage devices, is disclosed. The method includes providing a semiconductor substrate, ... | 10/31/2000 |
| 6103589 | High-voltage device substrate structure and method of fabrication A method for fabricating a high-voltage device substrate comprising the steps of forming a pad oxide layer and a mask layer over a substrate. Then, the pad oxide layer and the mask layer are patterned to define a region for a first ion implantation. Next,... | 08/15/2000 |
| 6104069 | Semiconductor device having an elevated active region formed in an oxide trench A process for forming a semiconductor device having an elevated active region is disclosed. The process includes forming a plurality of gate electrodes on the semiconductor substrate and disposing a thick oxide layer over the gate electrodes. A trench is ... | 08/15/2000 |
| 6083800 | Method for fabricating high voltage semiconductor device The present invention discloses a high voltage semiconductor device with high breakdown voltage without increment in area occupied an increase in the size of junction region. Each junction region includes: (i) a first impurity region of a first conductivi... | 07/04/2000 |
| 6078086 | Metal oxide semiconductor field effect transistor and method of manufacturing the same A MOSFET includes a semiconductor substrate of a first conductivity type including a field region and an active region; a gate insulating film on a portion of the active region, the gate insulating film having two edge parts and a mid-part, the two edge p... | 06/20/2000 |
| 6054743 | High voltage MOS transistor A high voltage MOS (Metal Oxide Semiconductor) transistor includes a semiconductor substrate of first conductivity type (P type). A pair of first diffused layers of second conductivity type (N type) are formed on the substrate. A pair of second diffused l... | 04/25/2000 |
| 6037229 | High-voltage device substrate structure and method of fabrication A method for fabricating a high-voltage device substrate comprising the steps of forming a pad oxide layer and a mask layer over a substrate. Then, the pad oxide layer and the mask layer are patterned to define a region for a first ion implantation. Next,... | 03/14/2000 |
| 5998832 | Metal oxide semiconductor device for an electro-static discharge circuit An improved metal oxide field effect transistor (MOSFET) provides an electro-static protection device with a high resistance to electro-static discharge. The electro-static discharge protection device has pre-gate heavily doped regions adjacent to the sou... | 12/07/1999 |
| 5973379 | Ferroelectric semiconductor device A ferroelectric semiconductor device (10) and a method of manufacturing the ferroelectric semiconductor device (10). The ferroelectric semiconductor device (10) has a layer (15) of ferroelectric material disposed on a semiconductor substrate (11) and a ga... | 10/26/1999 |
| 5929484 | High voltage semiconductor device The present invention discloses a high voltage semiconductor device with high breakdown voltage without increment in area occupied an increase in the size of junction region. Each junction region includes: (i) a first impurity region of a first conductivi... | 07/27/1999 |
| 5897358 | Semiconductor device having fluorine-enhanced transistor with elevated active regions and fabrication thereof A semiconductor device having a fluorine-enhanced transistor with elevated active regions and process for fabricating such a device is provided. A semiconductor device, consistent with one embodiment of the invention, includes a substrate and at least one... | 04/27/1999 |
| 5872038 | Semiconductor device having an elevated active region formed in an oxide trench and method of manufacture thereof A process for forming a semiconductor device having an elevated active region is disclosed. The process includes forming a plurality of gate electrodes on the semiconductor substrate and disposing a thick oxide layer over the gate electrodes. A trench is ... | 02/16/1999 |
| 5851844 | Ferroelectric semiconductor device and method of manufacture A ferroelectric semiconductor device (10) and a method of manufacturing the ferroelectric semiconductor device (10). The ferroelectric semiconductor device (10) has a layer (15) of ferroelectric material disposed on a semiconductor substrate (11) and a ga... | 12/22/1998 |
| 5846862 | Semiconductor device having a vertical active region and method of manufacture thereof A semiconductor device and method of manufacture thereof is provided. According to one embodiment, a semiconductor device is formed by forming a trench within a substrate. An oxide layer is formed within the trench and portions of the oxide layer are remo... | 12/08/1998 |
| 5811340 | Metal oxide semiconductor field effect transistor and method of manufacturing the same A MOSFET includes a semiconductor substrate of a first conductivity type including a field region and an active region; a gate insulating film on a portion of the active region, the gate insulating film having two edge parts and a mid-part, the two edge p... | 09/22/1998 |
| 5804485 | High density metal gate MOS fabrication process A high density metal gate metal-oxide semiconductor fabrication process to selectively and locally oxidize specific regions of a wafer without increasing the numbers of mask, so as to separately control the thickness of the oxide at the gate, P+ zones and... | 09/08/1998 |
| 5770880 | P-collector H.V. PMOS switch VT adjusted source/drain A PMOS device has an n-type body 12 and a triple source drain diffusion. A first drain region 14 is heavily p-doped to provide ohmic contact to the drain. A lightly doped drain region 16 extends to and beneath a portion of the gate 20. A third shallow mod... | 06/23/1998 |
| 5734185 | MOS transistor and fabrication process therefor An MOS transistor comprises a semiconductor substrate having a field region; a gate electrode formed on the semiconductor substrate through the intermediatry of a gate insulating film; and source/drain regions formed in the semiconductor substrate; wherei... | 03/31/1998 |
| 5646054 | Method for manufacturing MOS transistor of high breakdown voltage A high threshold voltage MOS transistor is described having a triple diffused drain structure in which low, medium and high concentration impurity layers overlap each other. The MOS transistor is manufactured according to a method including the steps of: ... | 07/08/1997 |
| 5571737 | Metal oxide semiconductor device integral with an electro-static discharge circuit An improved structure and process of fabricating a metal oxide field effect (MOSFET) which has a high resistance to electro-static discharge. The device has pre-gate heavily doped source and drain regions which overlap the gate electrode and the source an... | 11/05/1996 |
| 5547903 | Method of elimination of junction punchthrough leakage via buried sidewall isolation A method for forming MOSFET devices, with reduced exposure to source and drain leakage currents due to punchthrough phenomena, has been developed. The structure is fabricated using a buried insulator sidewall to isolate the source and drain regions. This ... | 08/20/1996 |
| 5547895 | Method of fabricating a metal gate MOS transistor with self-aligned first conductivity type source and drain regions and second conductivity type contact regions A method for manufacturing a CMOS transistor of integrated circuits having metal gates and self-aligned source and drain electrodes. The channel length can be precisely defined, and the leakage current can be reduced. Furthermore, the threshold voltage of... | 08/20/1996 |
| 5523246 | Method of fabricating a high-voltage metal-gate CMOS device A method of fabricating a high-voltage metal-gate CMOS device is disclosed. First, a semiconductor substrate of a first conductivity type having a well region of a second conductivity type is provided. Next, a barrier layer is formed and patterned to form... | 06/04/1996 |
| 5376568 | Method of fabricating high voltage complementary metal oxide semiconductor transistors A method for manufacturing CMOS transistors for integrated circuits which have metal gates and heavily doped source and drain electrode regions, thereby improving their resisting capability to a high voltage while reducing cycle time for manufacture. As a... | 12/27/1994 |
| 5312766 | Method of providing lower contact resistance in MOS transistors Germanium is used to significantly enhance the drift mobilities of minority carriers in the channels of N-channel and P-channel metal-oxide-semiconductor (MOS) transistors with silicon substrates. Germanium processing is also used to enhance the source/dr... | 05/17/1994 |
| 5296386 | Method of providing lower contact resistance in MOS transistor structures Germanium is used to significantly enhance the drift mobilities of minority carriers in the channels of N-channel and P-channel metal-oxide-semiconductor (MOS) transistors with silicon substrates. Germanium processing is also used to enhance the source/dr... | 03/22/1994 |
| 5296387 | Method of providing lower contact resistance in MOS transistor structures Germanium is used to significantly enhance the drift mobilities of minority carriers in the channels of N-channel and P-channel metal-oxide-semiconductor (MOS) transistors with silicon substrates. Germanium processing is also used to enhance the source/dr... | 03/22/1994 |
| 5235202 | Radiation hardened field dielectric utilizing BPSG A radiation hardened MOSFET is fabricated by forming a dielectric layer of boro-phosphosilicate glass (BPSG) over the field oxide layer of the MOSFET. The BPSG covers only a small part of the gate electrode of the MOSFET. The gate electrode of the MOSFET ... | 08/10/1993 |
| 5047820 | Semi self-aligned high voltage P channel FET An improved process to fabricate a high breakdown voltage MOSFET is disclosed. The process self-aligns the channel to the source and drain and semi self-aligns the gate electrode to the channel. The MOSFET also includes a boron field implant to extend the... | 09/10/1991 |
| 5024962 | Method for preventing auto-doping in the fabrication of metal gate CMOS devices A method of fabricating metal gate field effect transistors utilizing a rapid thermal oxidation process to form a sealing oxide which prevents auto-doping during the formation of the gate oxide.... | 06/18/1991 |
| 4520553 | Process for manufacturing an integrated insulated-gate field-effect transistor A process is described for manufacturing integrated insulated-gate field-effect transistors comprising contacts on both the source region and the drain region which are self-aligned with respect to the gate electrode. In this process the gate area and the... | 06/04/1985 |
| 4343078 | IGFET Forming method An insulated-gate field effect transistor for high speed operation is disclosed in which the internal resistance of the gate electrode is reduced and the stray gate capacitance is maintained at a low value. In one embodiment, the reduction of the internal... | 08/10/1982 |
| 4343079 | Self-registering method of manufacturing an insulated gate field-effect transistor A method of manufacturing an IGFET device in an entirely self-registering manner, in which on the semi-conductor body a narrow silicon nitride strip is formed which covers only the active region of the body and the width of which is substantially equal to... | 08/10/1982 |
