Class 257/E21.421 - With multiple gate, one gate having MOS structure and others having same or a different structure, i.e., non MOS, e.g., JFET gate (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.409. This
No. of patents: 59
Last issue date: 10/21/2008

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Number	Title	Issue Date
7439574	Silicon/oxide/nitride/silicon nonvolatile memory with vertical channels Provided are a silicon/oxide/nitride/oxide/silicon (SONOS) memory, a fabricating method thereof, and a memory programming method. The SONOS memory includes a substrate; a first insulating layer stacked on the substrate; a semiconductor layer, which is patterned on t...	10/21/2008
7368779	Hemi-spherical structure and method for fabricating the same Hemi-spherical structure and method for fabricating the same. A device includes discrete pillar regions on a substrate, and a pattern layer on the discrete support structures and the substrate. The pattern layer has hemi-spherical film regions on the discrete suppor...	05/06/2008
7341915	Method of making planar double gate silicon-on-insulator structures Methods are provided for forming a semiconductor device from a substrate comprising a bottom gate layer, a channel layer overlying the bottom gate layer, and a top gate structure formed over the channel layer. First, a hardmask comprising a first material interposed...	03/11/2008
7332425	Simultaneous deposition and etch process for barrier layer formation in microelectronic device interconnects The present invention provides a method of forming a interconnect barrier layer 100. In the method, physical vapor deposition of barrier material 200 is performed within an opening 140 located in a dielectric layer 135 of a substrate 1...	02/19/2008
7312129	Method for producing two gates controlling the same channel A semiconductor process and apparatus use a predetermined sequence of patterning and etching steps to etch a gate stack (62) formed over a substrate (11) and a first spacer structure (42), thereby forming etched gate structures (72, 74) t...	12/25/2007
7309885	PRAMs having a plurality of active regions located vertically in sequence and methods of forming the same There are provided PRAMS having a plurality of active regions located vertically in sequence and methods of forming the same. The PRAM and the method provide an approach to rapidly changing phase in a phase change layer pattern with a given design rule. A semiconduc...	12/18/2007
7306996	Methods of fabricating a semiconductor device having a metal gate pattern A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer st...	12/11/2007
7271069	Semiconductor device having a plurality of different layers and method therefor Mechanical stress control may be achieved using materials having selected elastic moduli. These materials may be selectively formed by implantation, may be provided as a plurality of buried layers interposed between the substrate and the active area, and may be form...	09/18/2007
7268394	JFET structure for integrated circuit and fabrication method Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in high voltage applications (e.g., having a breakdown voltage greater than about 20V). Additionally or alte...	09/11/2007
7256078	High mobility plane FinFETs with equal drive strength An integrated circuit structure has a buried oxide (BOX) layer above a substrate, and a first-type fin-type field effect transistor (FinFET) and a second-type FinFET above the BOX layer. The second region of the BOX layer includes a seed opening to the substrate. Th...	08/14/2007
7253037	Method of fabricating thin film transistor A method of fabricating a thin film transistor is provided. The method comprises first preparing a substrate and forming an amorphous silicon layer on the substrate. A catalyst construction is then positioned on the amorphous silicon layer and an anode and a cathode...	08/07/2007
7242040	Lateral trench field-effect transistors in wide bandgap semiconductor materials, methods of making, and integrated circuits incorporating the transistors A junction field effect transistor is described. The transistor is made from a wide bandgap semiconductor material. The device comprises source, channel, drift and drain semiconductor layers, as well as p-type implanted or Schottky gate regions. The source, channel,...	07/10/2007
7211870	Semiconductor device A semiconductor device capable of integrally controlling thresholds of gate electrodes of transistors present in a region of one-conductivity-type and transistors present in a region of an reverse-conductivity-type while suppressing noise propagation is provided. A ...	05/01/2007
7212437	Charge coupled EEPROM device and corresponding method of operation This invention provides a semiconductor memory device and a corresponding method of operation. The semiconductor memory device comprises a semiconductor substrate having a first conductivity; a plurality of gate structures for storing charge in a non-volatile manner...	05/01/2007
7192857	Method of forming a semiconductor structure with non-uniform metal widths A power transistor structure uses metal drain and source strips with non-uniform widths to reduce variations in current density across the power transistor structure. The reductions in current density, in turn, reduce the source-to-drain turn on resistance and maxim...	03/20/2007
7176073	Methods of forming memory cells having diodes and electrode plates connected to source/drain regions The invention pertains to thin film constructions comprising NVRAM devices built over a versatile substrate base. In particular aspects, a device includes a body region, and further include first and second diffusion regions formed in the body region. A channel regi...	02/13/2007
6841826	Low-GIDL MOSFET structure and method for fabrication A low-GIDL current MOSFET device structure and a method of fabrication thereof which provides a low-GIDL current. The MOSFET device structure contains a central gate conductor whose edges may slightly overlap the source/drain diffusions, and left and right side wing...	01/11/2005
6696725	Dual-gate MOSFET with channel potential engineering A semiconductor device with reduced hot carrier injection and punch through is formed with a dual gate electrode comprising edge conductive portions, a central conductive portion, and dielectric sidewall spacers formed between the edge conductive portions...	02/24/2004
6661057	Tri-level segmented control transistor and fabrication method A transistor is formed in an active area having a segmented gate structure. The segmented gate structure advantageously provides for dynamic control of a channel region formed within the transistor. Lightly doped source and drain (LDD) regions are formed ...	12/09/2003
6661055	Transistor in semiconductor devices The present invention relates to a transistor in a semiconductor device and method of manufacturing the same. According to the present invention, the transistor has an auxiliary electrode to which a voltage is applied apart from a gate electrode and forme...	12/09/2003
6649979	Method of manufacturing MOSFET and structure thereof A method of manufacturing an MOSFET. A substrate is provided. A trench filled with an insulating layer is formed in the substrate. The upper portion of the insulating layer is removed and then a spacer is formed on the side-wall of the trench. A sacrifici...	11/18/2003
6642591	Field-effect transistor A field-effect transistor includes a silicon substrate on which is formed a channel region, a source region and a drain region. A gate insulation layer of a transition metal oxide having a perovskite structure is formed over at least the channel region, a...	11/04/2003
6621118	MOSFET, semiconductor device using the same and production process therefor A MOSFET includes: a first conductivity type a semiconductor substrate having a trench formed in a surface area thereof, a gate electrode formed on the semiconductor substrate; and a trench gate electrode which is adjacent to the gate electrode and is bur...	09/16/2003
6596597	Method of manufacturing dual gate logic devices The present invention features double- or dual-gate logic devices that contain gate conductors that are consistently self-aligned and that have channels that are of constant width. The inventive process also provides a method of selectively etching german...	07/22/2003
6580137	Damascene double gated transistors and related manufacturing methods This invention provides the structure and fabrication process of a completely planar, Damascene double gated transistor. The structure has a novel self-aligned, hyper-abrupt retrograde body and a zero-parasitic, endwall gate-body connection. The structure...	06/17/2003
6548870	Semiconductor device In the semiconductor device, a first impurity region and a second impurity region are formed in a surface of a semiconductor substrate at a regular interval, and a gate insulating layer is formed on the semiconductor substrate between the first impurity r...	04/15/2003
6492212	Variable threshold voltage double gated transistors and method of fabrication The present invention provides a double gate transistor and a method for forming the same that facilitates the formation of different transistors having different threshold voltages. The embodiments of the present invention form transistors having differe...	12/10/2002
6433372	Dense multi-gated device design A multigated FET having reduced diffusion capacitance, self-compensating effective channel length, improved short channel effects control, and enhanced density. Forming the FET by providing a plurality of separated insulated gates on a substrate, includin...	08/13/2002
6420234	Short channel length transistor and method of fabricating the same Transistor and method for fabricating the same, which can form a channel length shorter than a lithography limit and adjust a substrate impurity concentration variably, the method including the steps of (1) depositing an insulating film on a semiconductor...	07/16/2002
6316296	Field-effect transistor and method of manufacturing same A dual gate structure field-effect transistor is manufactured by forming a trench in an SOI substrate comprised of a semiconductor support substrate, a buried insulation layer formed on the support substrate and an SOI semiconductor layer formed on the in...	11/13/2001
6285057	Semiconductor device combining a MOSFET structure and a vertical-channel trench-substrate field effect device A semiconductor device that provides for substrate current exiting a MOSFET structure, and hence the performance thereof, to be independently and controllably tuned. The semiconductor device includes a semiconductor substrate of a first conductivity type,...	09/04/2001
6262451	Electrode structure for transistors, non-volatile memories and the like An electrode structure for semiconductor devices includes first electrode material positioned in overlying relationship to the surface of a substrate so as to define a first side wall perpendicular thereto. A nonconductive side wall spacer is formed on th...	07/17/2001
6259142	Multiple split gate semiconductor device and fabrication method A semiconductor integrated circuit having a multiple split gate is forming using a first polysilicon layer and a second polysilicon layer to form alternating first and second gate electrodes within an active area. The alternating gate electrodes are elect...	07/10/2001
6236070	MES/MIS FET Disclosed is an improved field effect transistor (FET) employing both a metal-semiconductor (MES) gate and a metal-insulator-semiconductor (MIS) gate, which FET is particularly useful to provide amplification at microwave frequencies. The use of the MIS g...	05/22/2001
6218699	Semiconductor component with adjustable current amplification based on a tunnel-current-controlled avalanche breakdown The component has a channel zone and an oppositely doped zone in a semiconductor substrate. The channel zone and a peripheral region of the first doped zone are separated by a gate dielectric from an overlying channel gate electrode. The first doped zone ...	04/17/2001
6090693	Transistors having controlled conductive spacers, uses of such transistors and methods of making such transistors A transistor structure includes an insulated conductive gate spacer or a conductive layer under a nonconductive spacer, together forming a composite spacer, which is contacted and driven separately from the conventional gate of the transistor. The gate sp...	07/18/2000
6051470	Dual-gate MOSFET with channel potential engineering A semiconductor device with reduced hot carrier injection and punch through is formed with a dual gate electrode comprising edge conductive portions, a central conductive portion, and dielectric sidewall spacers formed between the edge conductive portions...	04/18/2000
6031266	Semiconductor device with conductive sidewall film In the MOS FET semiconductor device having a LDD structure, a polysilicon layer of which a side wall film is formed is provided, the polysilicon layer is made conductive by doping an impurity by ion-implantation. The side wall film of conductive polysilic...	02/29/2000
6005267	MES/MIS FET with split-gate RF input Disclosed is an improved field effect transistor (FET) employing both a metal-semiconductor (MES) gate and a metal-insulator-semiconductor (MIS) gate, which FET is particularly useful to provide amplification at microwave frequencies. The use of the MIS g...	12/21/1999
6005273	Transistors having controlled conductive spacers, uses of such transistors and methods of making such transistors A transistor structure includes an insulated conductive gate spacer or a conductive layer under a nonconductive spacer, together forming a composite spacer, which contacted and driven separately from the conventional gate of the transistor. The gate space...	12/21/1999

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Class 257/E21.421 - With multiple gate, one gate having MOS structure and others having same or a different structure, i.e., non MOS, e.g., JFET gate (EPO)