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| Number | Title | Issue Date |
| 7378708 | Transistor having a protruded drain A field effect transistor includes a gate that is formed in a channel region of an active region defined on a substrate. A source is formed at a first surface portion of the active region that is adjacently disposed at a first side face of the gate. A drain is forme... | 05/27/2008 |
| 7345341 | High voltage semiconductor devices and methods for fabricating the same High voltage semiconductor devices and methods for fabricating the same are provided. An exemplary embodiment of a semiconductor device capable of high-voltage operation, comprising a substrate comprising a first well formed therein. A gate stack is formed overlying... | 03/18/2008 |
| 7301201 | High voltage device having polysilicon region in trench and fabricating method thereof A high voltage device prevents or minimizes the lowering of a maximum operating voltage range. Bulk resistances of the drift regions are reduced by forming trenches within the drift regions and filling the trenches with conductive polysilicon layers. The polysilicon... | 11/27/2007 |
| 7230299 | Power switch structure with low RDSon and low current limit and method In one embodiment, a power switch device (33) includes a first MOSFET device 41 and a second MOSFET device (42). A split gate structure (84) including a first gate electrode (48,87) controls the first MOSFET device (41). A s... | 06/12/2007 |
| 7125777 | Asymmetric hetero-doped high-voltage MOSFET (AHMOS) An asymmetric hetero-doped metal oxide (AH2MOS) semiconductor device includes a substrate and an insulated gate on the top of the substrate disposed between a source region and a drain region. On one side of the gate, heterodoped tub and source regions ar... | 10/24/2006 |
| 7122861 | Semiconductor device and manufacturing method thereof The present invention relates to a semiconductor device including a high withstand voltage MOS transistor and a manufacturing method thereof. The semiconductor device according to the present invention includes a MOS transistor in which a second-conductivity type so... | 10/17/2006 |
| 6900101 | LDMOS transistors and methods for making the same LDMOS transistor devices and fabrication methods are provided, in which additional dopants are provided to region of a substrate near a thick dielectric between the channel and the drain to reduce device resistance without significantly impacting breakdown voltage. ... | 05/31/2005 |
| 6699740 | Method for manufacturing a lateral double-diffused MOS transistor having stable characteristics and equal drift length A semiconductor device including a P-type semiconductor layer; an N-type first well on the surface of the semiconductor layer; a P-type second well on the surface of the first well; an N-type source region on the surface of the second well; and an N-type ... | 03/02/2004 |
| 6696323 | Method of manufacturing semiconductor device having trench filled up with gate electrode In a semiconductor device, a p-type base region is provided in an n- -type substrate to extend from a principal surface of the substrate in a perpendicular direction to the principal surface. An n+ -type source region extends in the ... | 02/24/2004 |
| 6677642 | Field effect transistor structure and method of manufacture A field effect transistor structure is formed with a body semiconductor layer (5) having source (9), body (7), drift region and drain (11). An upper semiconductor layer (21) is separated from the body by an oxide layer (17). The upper semiconductor layer ... | 01/13/2004 |
| 6670685 | Method of manufacturing and structure of semiconductor device with floating ring structure A high voltage semiconductor device includes a drain region disposed within a semiconductor substrate. The semiconductor device further includes a field oxide layer disposed outwardly from the drain region of the semiconductor substrate. The semiconductor... | 12/30/2003 |
| 6664593 | Field effect transistor structure and method of manufacture A field effect transistor structure is formed with a body semiconductor layer (1) having source (3), channel (7), drift region (9) and drain (5). An upper metallisation layer (15, 17) is separated from the body by an oxide layer (11). The upper metallisat... | 12/16/2003 |
| 6639277 | High-voltage transistor with multi-layer conduction region A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sa... | 10/28/2003 |
| 6633065 | High-voltage transistor with multi-layer conduction region A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sa... | 10/14/2003 |
| 6624470 | Semiconductor device and a method for manufacturing same A semiconductor device, and method for manufacturing the same, manufactured by a simpler process, compared to a conventional trench lateral power MOSFET for a withstand voltage of 80 V, having a smaller device pitch and lower on-resistance per unit area a... | 09/23/2003 |
| 6580131 | LDMOS device with double N-layering and process for its manufacture The tradeoff between breakdown voltage and on-resistance for LDMOS devices has been improved by having two epitaxial N-regions instead of the single epitaxial N-region that is used by devices of the prior art. The resistivities and thicknesses of these tw... | 06/17/2003 |
| 6570219 | High-voltage transistor with multi-layer conduction region A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sa... | 05/27/2003 |
| 6559504 | Lateral double diffused MOS transistor To increase the withstand voltage and reduce ON-state resistance, a semiconductor device provided with a gate electrode formed on a semiconductor substrate via a gate insulating film, an LP layer (a P-type body region) formed so that the LP layer is adjac... | 05/06/2003 |
| 6509220 | Method of fabricating a high-voltage transistor A method for making a high voltage insulated gate field-effect transistor with one or more JFET conduction channels comprises successively implanting a dopant of a first conductivity type in a first epitaxial layer of a second conductivity type so as to f... | 01/21/2003 |
| 6489190 | Method of fabricating a high-voltage transistor A method for making a high voltage insulated gate field-effect transistor with multiple JFET conduction channels comprises successively implanting a dopant of a first conductivity type in a first substrate of a second conductivity type so as to form a fir... | 12/03/2002 |
| 6486034 | Method of forming LDMOS device with double N-layering The tradeoff between breakdown voltage and on-resistance for LDMOS devices has been improved by having two epitaxial N- regions instead of the single epitaxial N- region that is used by devices of the prior art. The resistivities and thicknesses of these ... | 11/26/2002 |
| 6468847 | Method of fabricating a high-voltage transistor A method for making a high voltage insulated gate field-effect transistor with multiple JFET conduction channels comprises successively implanting a dopant of a first conductivity type in a first substrate of a second conductivity type so as to form a fir... | 10/22/2002 |
| 6468870 | Method of fabricating a LDMOS transistor A method of manufacturing a LDHOS transistor having a dielectric block under the gate electrode. A high voltage well, low voltage well (LV PW), and field oxide regions having bird beaks are provided in a substrate and overlay the high voltage well and the... | 10/22/2002 |
| 6465869 | Compensation component and process for producing the compensation component A compensation component includes a drift path formed of p-conducting and n-conducting layers which are led around or along a trench. A process for producing the compensation component is also provided.... | 10/15/2002 |
| 6452222 | MIS type semiconductor device and method for manufacturing the same A horizontal type DMISFET is remarkably improved in its endurance of an over-voltage applied to a drain electrode thereof. In this MIS type semiconductor device, an N+ -type source region assuming an octagonal-shaped configuration in plan view ... | 09/17/2002 |
| 6448620 | Semiconductor device and process for producing the same To provide a semiconductor device having a large allowable current, a demanded withstand voltage, and small output capacitance and resistance, the semiconductor device comprises a semiconductor layer formed on a semiconductor substrate, and the semiconduc... | 09/10/2002 |
| 6445038 | Silicon on insulator high-voltage switch An SOI high-voltage switch with an FET structure, in which a drift zone of one conductivity type is provided between a gate electrode and a drain electrode in the drain region. Pillar-like trenches in the form of a grid are incorporated in the drift zone ... | 09/03/2002 |
| 6426258 | Method of manufacturing a semiconductor integrated circuit device A method of manufacturing a semiconductor integrated circuit device comprises forming a gate insulating film on a surface of a semiconductor substrate of a first conductivity type, forming a polycrystal silicon film on the gate insulating film, etching th... | 07/30/2002 |
| 6424005 | LDMOS power device with oversized dwell An LDMOS device (10, 20, 50, 60) that is made with minimal feature size fabrication methods, but overcomes potential problems of misaligned Dwells (13). The Dwell (13) is slightly overstated so that its n-type dopant is implanted past the source edge of t... | 07/23/2002 |
| 6399468 | Semiconductor device and method of manufacturing the same To increase the withstand voltage and reduce ON-state resistance, a semiconductor device provided with a gate electrode formed on a semiconductor substrate via a gate insulating film, an LP layer (a P-type body region) formed so that the LP layer is adjac... | 06/04/2002 |
| 6373110 | Semiconductor device having high breakdown voltage A power field effect transistor includes a bulge portion and/or a constricted portion in at least one of the heavily doped drain contact region and the lightly doped channel forming region, and heavily doped source regions are formed in the lightly doped ... | 04/16/2002 |
| 6346451 | Laterial thin-film silicon-on-insulator (SOI) device having a gate electrode and a field plate electrode A lateral thin-film Silicon-On-Insulator (SOI) device includes a semiconductor substrate, a buried insulating layer on the substrate and a lateral transistor device in an SOI layer on the buried insulating layer and having a source region of a first condu... | 02/12/2002 |
| 6310378 | High voltage thin film transistor with improved on-state characteristics and method for making same The present invention is directed to an SOI LDMOS device having improved current handling capability, particularly in the source-follower mode, while maintaining an improved breakdown voltage capability. The improvement in current handling capability is a... | 10/30/2001 |
| 6303954 | Semiconductor device with a high-voltage component in semiconductor on insulator A semiconductor device comprises a semiconductor layer on an insulator film that is contiguous to a semiconductor substrate. A component, such as a high-voltage diode, forming region is provided in the semiconductor layer and electrically insulated from o... | 10/16/2001 |
| 6242787 | Semiconductor device and manufacturing method thereof A semiconductor device including a reduced surface field strength type LDMOS transistor which can prevent the breakdown of elements at channel formation portions when a reverse voltage is applied to its drain. A P well and an N well are formed in an N-typ... | 06/05/2001 |
| 6236084 | Semiconductor integrated circuit device having double diffusion insulated gate field effect transistor To provide a lateral double diffusion insulated gate field effect transistor with high driving current and low source-drain withstand voltage without receiving the influence of process fluctuation. Without shortening a gate electrode 10 as compared with c... | 05/22/2001 |
| 6215152 | MOSFET having self-aligned gate and buried shield and method of making same A MOSFET has a buried shield plate under the gate and over the drain with the gate being formed on the periphery of the buried shield plate as a self-aligned structure with minimal or no overlap of the gate over the shield plate. Methods of fabricating th... | 04/10/2001 |
| 6207994 | High-voltage transistor with multi-layer conduction region A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sa... | 03/27/2001 |
| 6190978 | Method for fabricating lateral RF MOS devices with enhanced RF properties Methods of fabrication of a lateral RF MOS device having a non-diffusion connection between source and substrate are disclosed. In one embodiment, the lateral RF MOS device has an interdigitated silicided gate structure. In another embodiment, the lateral... | 02/20/2001 |
| 6171912 | Method of manufacturing a semiconductor device comprising a field effect transistor The invention relates to a method of manufacturing a field effect transistor, in particular a discrete field effect transistor, comprising a source region (1) and a drain region (2) and, between said regions, a channel region (4) above which a gate region... | 01/09/2001 |
